DF2170VTE33 Renesas Electronics America, DF2170VTE33 Datasheet - Page 235

• Manufacturer Part Number: DF2170VTE33
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2170VTE33; HD64F2170VTE33

7.4.11
Examples of operation timings for various conditions in each mode are shown. The contention
with other bus master is described by using the CPU external bus cycle as an example.
Auto Request/Cycle Steal Mode/Normal Transfer Mode: When the DA bit is set to 1 in
DMMDR, an DMA transfer cycle is started a minimum of three cycles later. There is a one-cycle
bus release interval between the end of a one-transfer-unit DMA cycle and the start of the next
transfer.
If there is a transfer request for another channel of higher priority, the transfer request by the
original channel is held pending, and transfer is performed on the higher-priority channel from the
next transfer. Transfer on the original channel is resumed on completion of the higher-priority
channel transfer.
Figures 7.32 to 7.34 show operation timing examples for various conditions.
• No contention/dual address mode (see figure 7.32)
• CPU cycles/single address mode (see figure 7.33)
• Contention with another channel/single address mode (see figure 7.34)
φ pin
Bus cycle
CPU
operation
DA bit
Examples of Operation Timing in Each Mode
DA = 1
write
Figure 7.32 Auto Request/Cycle Steal Mode/Normal Transfer Mode
0
Bus release
1
3 cycles
Sleep
(No Contention/Dual Address Mode)
DMA
read
DMA
write
1 cycle
Bus
release
DMA
read
Rev. 2.00, 03/04, page 201 of 534
DMA
write
Bus
release
Last transfer cycle
DMA
read
DMA
write
0