DF2170VTE33 Renesas Electronics America, DF2170VTE33 Datasheet - Page 58

• Manufacturer Part Number: DF2170VTE33
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2170VTE33; HD64F2170VTE33

2.4.4
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.
Rev. 2.00, 03/04, page 24 of 534
Bit
7
6
5
4
3
2
1
Bit Name
I
UI
H
U
N
Z
V
Condition-Code Register (CCR)
Initial
Value
1
Undefined R/W
Undefined R/W
Undefined R/W
Undefined R/W
Undefined R/W
Undefined R/W
R/W
R/W
Description
Interrupt Mask Bit
Masks interrupts other than NMI when set to 1. NMI is
accepted regardless of the I bit setting. The I bit is set to
1 at the start of an exception-handling sequence. For
details, refer to section 5, Interrupt Controller.
Can be written to and read from by software using the
LDC, STC, ANDC, ORC, and XORC instructions.
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B or
NEG.B instruction is executed, this flag is set to 1 if there
is a carry or borrow at bit 3, and cleared to 0 otherwise.
When the ADD.W, SUB.W, CMP.W, or NEG.W
instruction is executed, the H flag is set to 1 if there is a
carry or borrow at bit 11, and cleared to 0 otherwise.
When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is
executed, the H flag is set to 1 if there is a carry or
borrow at bit 27, and cleared to 0 otherwise.
Can be written to and read from by software using the
LDC, STC, ANDC, ORC, and XORC instructions.
Negative Flag
Stores the value of the most significant bit of data as a
sign bit.
Zero Flag
Set to 1 to indicate zero data, and cleared to 0 to indicate
non-zero data.
Overflow Flag
Set to 1 when an arithmetic overflow occurs, and cleared
to 0 otherwise.
User Bit or Interrupt Mask Bit
Half-Carry Flag
User Bit