DF2170VTE33 Renesas Electronics America, DF2170VTE33 Datasheet - Page 92
DF2170VTE33
Manufacturer Part Number
DF2170VTE33
Description
MCU 3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2170BVTE33V.pdf
(572 pages)
Specifications of DF2170VTE33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
SCI, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2170VTE33
HD64F2170VTE33
HD64F2170VTE33
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2170VTE33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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4.3.2
If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx: 32, SP).
4.3.3
After a reset is cancelled, the module stop control register (MSTPCR) is initialized, and all
modules except the DMAC operate in module stop mode. Therefore, the registers of on-chip
peripheral modules cannot be read from or written to. To read from and write to these registers,
clear module stop mode.
Rev. 2.00, 03/04, page 58 of 534
φ
RES
Internal address bus
Internal read signal
Internal write signal
Internal data bus
(1), (3)
(2), (4)
Interrupts after Reset
On-Chip Peripheral Modules after Reset is Cancelled
(5)
(6)
Reset exception handling vector address ((1) = H'000000, (3) = H'000002)
Start address (contents of reset exception handling vector address)
Start address ((5) = (2)(4))
First program instruction
Figure 4.1 Reset Sequence
(1)
(2)
Vector
fetch
High
(4)
processing
(3)
Internal
Prefetch of first program
instruction
(5)
(6)
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