HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 159

• Manufacturer Part Number: HD6417727F100C
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100C

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Physical Address Space: The SH7727 supports a 32-bit physical address space, but the upper 3
bits are actually ignored and treated as a shadow. See section 12, Bus State Controller (BSC), for
details.
Address Translation: When the MMU is enabled, the logical address space is divided into units
called pages. Physical addresses are translated in page units. Address translation tables in external
memory hold information such as the physical address that corresponds to the logical address and
memory protection codes. When an access to an area other than P4 occurs, if the accessed logical
address belongs to area P1 or P2 there is no TLB access and the physical address is uniquely
defined. If it belongs to area P0, P3 or U0, the TLB is searched by logical address and, if that
logical address is registered in the TLB, the access hits the TLB. The corresponding physical
H'80000000
H'A0000000
H'C0000000
H'E0000000
H'FFFFFFFF
H'00000000
(write-back/write-through)
(write-back/write-through)
(write-back/write-through)
0.5-Gbyte fixed physical
0.5-Gbyte control space,
0.5-Gbyte virtual space,
2-Gbyte virtual space,
space, cacheable
Privileged mode
0.5-Gbyte fixed
physical space,
non-cacheable
non-cacheable
cacheable
cacheable
Figure 3.2 Logical Address Space Mapping
Area P0
Area P1
Area P2
Area P3
Area P4
H'00000000
H'80000000
H'FFFFFFFF
Section 3 Memory Management Unit (MMU)
Rev.6.00 Mar. 27, 2009 Page 101 of 1036
(write-back/write-through)
2-Gbyte virtual space,
Address error
Address error
User mode
cacheable
REJ09B0254-0600
Area U0
Area Uxy
(present
only when
SR.DSP=1)