HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 20

• Manufacturer Part Number: HD6417727F100C
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100C

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

3.4
3.5
3.6
3.7
Section 4 Exception Handling
4.1
4.2
4.3
4.4
4.5
Rev.6.00 Mar. 27, 2009 Page xviii of lvi
REJ09B0254-0600
3.3.1
3.3.2
3.3.3
3.3.4
MMU Functions................................................................................................................ 111
3.4.1
3.4.2
3.4.3
3.4.4
MMU Exceptions.............................................................................................................. 116
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.5.6
Memory-Mapped TLB...................................................................................................... 124
3.6.1
3.6.2
3.6.3
Usage Notes ...................................................................................................................... 128
Overview........................................................................................................................... 131
4.1.1
4.1.2
Exception Handling Function ........................................................................................... 131
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
Register Description.......................................................................................................... 138
Exception Handling Operation.......................................................................................... 139
4.4.1
4.4.2
4.4.3
Individual Exception Operations....................................................................................... 140
4.5.1
Configuration of the TLB .................................................................................... 105
TLB Indexing....................................................................................................... 107
TLB Address Comparison ................................................................................... 108
Page Management Information............................................................................ 110
MMU Hardware Management ............................................................................. 111
MMU Software Management .............................................................................. 111
MMU Instruction (LDTLB)................................................................................. 112
Avoiding Synonym Problems .............................................................................. 113
TLB Miss Exception ............................................................................................ 116
TLB Protection Violation Exception ................................................................... 117
TLB Invalid Exception ........................................................................................ 118
Initial Page Write Exception ................................................................................ 119
Processing Flow in Event of MMU Exception (Same Processing Flow
for Address Error) ................................................................................................ 121
MMU Exception in Repeat Loop......................................................................... 123
Address Array ...................................................................................................... 125
Data Array............................................................................................................ 125
Usage Examples................................................................................................... 127
Features................................................................................................................ 131
Register Configuration......................................................................................... 131
Exception Handling Flow .................................................................................... 131
Exception Handling Vector Addresses ................................................................ 132
Acceptance of Exceptions.................................................................................... 134
Exception Codes .................................................................................................. 136
Exception Request Masks .................................................................................... 137
Returning from Exception Handling.................................................................... 138
Reset .................................................................................................................... 139
Interrupts.............................................................................................................. 139
General Exceptions .............................................................................................. 140
Resets ................................................................................................................... 140
......................................................................................... 131