HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 523

• Manufacturer Part Number: HD6417727F100C
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100C

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

16.2.8
The year counter (RYRCNT) is an 8-bit read/write register used for setting/counting in the BCD-
coded year section of the RTC. The least significant 2 digits of the western calendar year are
displayed. The count operation is performed by a carry for each year of the month counter.
The settable range is 00 to 99 in decimal. If other values are set, correct operation is not provided.
When modifying RYRCNT, check that the count operation is halted with the START bit in RCR2.
RYRCNT is not initialized by a power-on reset or manual reset, or in standby mode, and the
operation is continued.
Leap years are recognized by dividing the year counter value by 4 and obtaining a fractional result
of 0. Note that a counter value of 00 is treated as a leap year.
16.2.9
The second alarm register (RSECAR) is an 8-bit read/write alarm register that corresponds to the
BCD-coded second section counter RSECCNT of the RTC. When the ENB bit is set to 1in
RSECAR, the RSECAR value and RSECCNT value are compared. In this way, the RSECAR,
RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR registers are checked, and when the
ENB bit is set to 1, the alarm register and the corresponding counter are compared. If all values in
the specified alarm registers and the corresponding counters match, an RTC alarm interrupt is
generated.
The settable range is “00 to 59 in decimal + ENB bit”. If other values are set, correct operation is
not provided.
Only the ENB bit in RSECAR is initialized to 0 by a power-on reset, and the other bits are not
initialized. The RSECAR contents are retained after a manual reset or in standby mode.
Initial value:
Initial value:
Year Counter (RYRCNT)
Second Alarm Register (RSECAR)
R/W:
R/W:
Bit:
Bit:
ENB
R/W
R/W
—
7
7
0
R/W
R/W
—
—
6
6
10 years
10 seconds
R/W
R/W
—
—
5
5
R/W
R/W
—
—
4
4
Rev.6.00 Mar. 27, 2009 Page 465 of 1036
R/W
R/W
—
—
3
3
Section 16 Realtime Clock (RTC)
R/W
R/W
—
—
2
2
1 second
1 year
REJ09B0254-0600
R/W
R/W
—
—
1
1
R/W
R/W
—
—
0
0