HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 787

• Manufacturer Part Number: HD6417727F100C
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100C

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

24.2.2
HcControl Register (H'04000404)
The HcControl register defines the operation mode for the host controller. Most of bits of this
register are amended only by the host controller driver other than HostController Function State
and Remote Wakeup Command.
Register: HcControl
Bits
31–11
10
9
8
HcControl
Reset
0h
0b
0b
0b
R/W
—
R/W
R/W
R/W
Offset: 04–07
Description
Reserved. Read/Write 0's
RemoteWakeupEnable (RWE)
This bit is used by HCD to enable/disable the remote wakeup
function at the same time as the detection of an upstream
resume signal. This function is not supported. Be sure to write
0.
RemoteWakeupConnected (RWC)
This bit indicates whether the host controller supports a remote
wakeup signal or not. When the remote wakeup is supported
and used in the system, the host controller must set this bit
between POST in the system firmware. The host controller
clears the bit at the same time of the hardware reset, however,
does not change at the same time as the software reset. The
remote wakeup signal to the system of the host is specific for
the host bus, so it is not described in this specification.
0: Remote wakeup signal is not supported. (initial value)
1: Remote wakeup signal is supported.
InterruptRouting (IR)
This bit determines the routing of interrupts generated by the
event registered in HcInterruptStatus. HCD clears this bit at the
same time as the hardware reset, however, does not clear at
the same time as the software reset. HCD uses this bit as a tag
to indicate the ownership of the host controller.
0: All interrupts are routed to normal bus interrupt mechanism.
1: Interrupts are routed to SMI.
(initial value)
Rev.6.00 Mar. 27, 2009 Page 729 of 1036
Section 24 USB HOST Module
REJ09B0254-0600