HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 985

• Manufacturer Part Number: HD6417727F100C
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100C

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

31.4.3
An H-UDI reset is executed by setting an H-UDI reset assert command in SDIR. An H-UDI reset
is of the same kind as a power-on reset. An H-UDI reset is released by inputting an H-UDI reset
negate command.
31.4.4
The H-UDI interrupt function generates an interrupt by setting a command from the H-UDI in the
SDIR. An H-UDI interrupt is a general exception/interrupt operation, resulting in a branch to an
address based on the VBR value plus offset, and return by the RTE instruction. This interrupt
request has a fixed priority level of 15.
H-UDI interrupts are not accepted in sleep mode or standby mode.
31.4.5
Setting the command from H-UDI to SDIR allows to set the H-UDI pins to the bypass mode that
conforms with the JTAG standard.
31.4.6
It is possible to recover from sleep mode by setting a command (0001) from the H-UDI in SDIR.
SDIR
Chip internal
reset
CPU state
H-UDI Reset
H-UDI Interrupt
Bypass
Using H-UDI to Recover from Sleep Mode
H-UDI reset assert
Figure 31.3 H-UDI Reset
H-UDI reset negate
Section 31 User-Debugging Interface (H-UDI)
Rev. 5.00 Dec 12, 2005 page 927 of 1034
Branch to H'A0000000
REJ09B0254-0500