HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 636

• Manufacturer Part Number: HD6417727F100C
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100C

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 19 Serial Communication Interface with FIFO (SCIF)
Bit 4—Break Detection (BRK): Indicates that a break signal is detected in received data.
Bit 4: BRK
0
1
Note: * When a break is detected, transfer of the received data (H'00) to SCFRDR2 stops after
Bit 3—Framing Error (FER): Indicates a framing error in the data read from the receive FIFO
data register 2 (SCFRDR2).
Bit 3: FER
0
1
Bit 2—Parity Error (PER): Indicates a parity error in the data read from the receive FIFO data
register 2 (SCFRDR2).
Bit 2: PER
0
1
Rev.6.00 Mar. 27, 2009 Page 578 of 1036
REJ09B0254-0600
detection. When the break ends and the receive signal becomes mark 1, the transfer of
the received data resumes. The received data of a frame in which a break signal is
detected is transferred to SCFRDR2. After this, however, no received data is transferred
until a break ends with the received signal being mark 1 and the next data is received.
Description
No break signal is being received.
BRK is cleared to 0 when the chip is reset or enters standby mode, or software
reads BRK after it has been set to 1, then writes 0 in BRK.
The break signal is received.*
BRK is set to 1 when data including a framing error is received and a framing
error occurs with space 0 in the subsequent received data.
Description
No receive framing error occurred in the data read from SCFRDR2. (Initial value)
FER is cleared to 0 when the chip is power-on reset or enters standby mode, or
when no framing error is present in the data read from SCFRDR2.
A receive framing error occurred in the data read from SCFRDR2.
FER is set to 1 when a framing error is present in the data read from SCFRDR2.
Description
No receive parity error occurred in the data read from SCFRDR2.
PER is cleared to 0 when the chip is power-on reset or enters standby mode, or
when no parity error is present in the data read from SCFRDR2.
A receive parity error occurred in the data read from SCFRDR2.
PER is set to 1 when a parity error is present in the data read from SCFRDR2.
(Initial value)
(Initial value)