HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 257

IC SUPERH MPU ROMLESS 240QFP

HD6417727F100C

Manufacturer Part Number
HD6417727F100C
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417727F100C

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417727F100C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
7.4.2
When processing multiple interrupts, an interrupt handler should include the following
procedures:
1. Branch to a specific interrupt handler corresponding to a code set in INTEVT and INTEVT2.
2. Clear the cause of the interrupt in each specific handler.
3. Save SSR and SPC to the memory.
4. Clear the BL bit in SR, and set the accepted interrupt level in the interrupt mask bits in SR.
5. Handle the interrupt.
6. Execute the RTE instruction.
When these procedures are followed in order, an interrupt of higher priority than the one being
handled can be accepted after clearing BL in step 4.
7.5
The time from generation of an interrupt request until interrupt exception handling is performed
and fetching of the first instruction of the exception handler is started (the interrupt response time)
is shown in table 7.8. Figure 7.4 shows an example of pipeline operation when an IRL interrupt is
accepted. When SR.BL is 1, interrupt exception handling is masked, and is kept waiting until
completion of an instruction that clears BL to 0.
The code in INTEVT and INTEVT2 can be used as a branch-offset for branching to the
specific handler.
Multiple Interrupts
Interrupt Response Time
Rev.6.00 Mar. 27, 2009 Page 199 of 1036
Section 7 Interrupt Controller (INTC)
REJ09B0254-0600

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