HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 451

IC SUPERH MPU ROMLESS 240QFP

HD6417727F100C

Manufacturer Part Number
HD6417727F100C
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417727F100C

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417727F100C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit 1—Transfer End (TE): TE is set to 1 when data transfer ends by the count specified in
DMATCR. At this time, if the IE bit is set to 1, an interrupt request is generated.
Before this bit is set to 1, if data transfer ends due to an NMI interrupt, a DMAC address error, or
clearing the DE bit or the DME bit in DMAOR, this bit is not set to 1. Even if the DE bit is set to
1 while this bit is set to 1, transfer is not enabled.
Bit 1: TE
0
1
Bit 0—DMAC Enable (DE): DE enables channel operation.
Bit 0: DE
0
1
If the auto request is specified in RS3 to RS0, transfer starts when this bit is set to 1. For an
external request or an on-chip module request, transfer starts if a transfer request is generated after
this bit is set to 1. Clearing this bit during transfer can terminate transfer.
Even if the DE bit is set, transfer is not enabled when the TE bit is 1, the DME bit in DMAOR is
0, or the NMIF bit or AE bit in DMAOR is 1.
Description
Data transfer does not end by the count specified in DMATCR
Clear condition: Writing 0 after TE = 1 read at power-on reset or manual reset
Data transfer ends by the specified count
Description
Disables channel operation
Enables channel operation
Section 14 Direct Memory Access Controller (DMAC)
Rev.6.00 Mar. 27, 2009 Page 393 of 1036
REJ09B0254-0600
(Initial value)
(Initial value)

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