HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 909

IC SUPERH MPU ROMLESS 240QFP

HD6417727F100C

Manufacturer Part Number
HD6417727F100C
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417727F100C

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417727F100C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
27.6
Each pin has an input pullup MOS, which is controlled by Port G Control Register (PGCR) in
PFC
27.6.1
Note: * Undefined
Port G Data Register (PGDR) is an 8-bit read register that stores data for pins PTG7 and PTG5 to
PTG0. PG7DT and PTG5DT to PG0DT bit corresponds to PTG7 and PTG5 to PTG0 pin. When
the pin function is general input port, if the port is read, the corresponding pin level is read. Table
27.5 shows the function of PGDR.
When ASEMD0 is equal to 1, after PGDR is initialized by a power-on reset, the general input port
function (pullup MOS: on) is set as the initial pin function, and the corresponding pin levels are
fetched.
Table 27.5 Read/Write Operation of the Port G Data Register (PGDR)
PGnMD1 PGnMD0 Pin State
0
1
Note: * Operation cannot be guaranteed when this bit it set to “reserved.”
.
Initial value:
Port G
Port G Data Register (PGDR)
0
1
0
1
R/W:
Bit:
PG7DT
Other function H’00
Reserved*
Input (Pullup
MOS: on)
Input (Pullup
MOS: off)
R
7
*
R
6
*
Read
Pin state
Pin state
PG5DT
R
5
*
PG4DT
Write
Ignored (no affect on pin state)
Ignored (no affect on pin state)
Ignored (no affect on pin state)
R
4
*
Rev.6.00 Mar. 27, 2009 Page 851 of 1036
PG3DT
R
3
*
PG2DT
R
2
*
Section 27 I/O Ports
REJ09B0254-0600
PG1DT
R
1
*
(n = 0 to 5, 7)
PG0DT
R
0
*

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