UPD78F0513AMC-GAA-AX Renesas Electronics America, UPD78F0513AMC-GAA-AX Datasheet - Page 290

• Manufacturer Part Number: UPD78F0513AMC-GAA-AX
• Description: MCU 8BIT 38PIN SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AMC-GAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
(a) 16-bit timer mode control register 0n (TMC0n)
(b) Capture/compare control register 0n (CRC0n)
(c) 16-bit timer output control register 0n (TOC0n)
(d) Prescaler mode register 0n (PRM0n)
(e) 16-bit timer counter 0n (TM0n)
(f) 16-bit capture/compare register 00n (CR00n)
(g) 16-bit capture/compare register 01n (CR01n)
Remark n = 0:
ES1n1
0
0
0
0
By reading TM0n, the count value can be read.
If M is set to CR00n, the interval time is as follows.
• Interval time = (M + 1) × Count clock cycle
Setting CR00n to 0000H is prohibited.
Usually, CR01n is not used for the interval timer function. However, a compare match interrupt (INTTM01n) is
generated when the set value of CR01n matches the value of TM0n.
Therefore, mask the interrupt request by using the interrupt mask flag (TMMK01n).
n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products
OSPT0n
ES1n0
0
0
0
0
Figure 7-18. Example of Register Settings for Interval Timer Operation
78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2,
78K0/KD2 products
OSPE0n
ES0n1
0
0
0
0
TOC0n4
ES0n0
0
0
0
0
TMC0n3 TMC0n2 TMC0n1
LVS0n
1
0
0
3
0
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
CRC0n2 CRC0n1 CRC0n0
LVR0n
1
0
0
0
2
TOC0n1
PRM0n1 PRM0n0
0
0
0/1
0
OVF0n
TOE0n
0
0
0/1
0
Clears and starts on match
between TM0n and CR00n.
CR00n used as
compare register
Selects count clock
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