UPD78F0513AMC-GAA-AX Renesas Electronics America, UPD78F0513AMC-GAA-AX Datasheet - Page 548

• Manufacturer Part Number: UPD78F0513AMC-GAA-AX
• Description: MCU 8BIT 38PIN SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AMC-GAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
(Master)
CSIAE0
SCKA0
SCKA0
(Slave)
BUSY0
ACSIIF
ERRF0
SOA0
(c) Bit shift detection by busy signal
SIA0
During automatic transmission/reception, a bit shift of the serial clock of the slave device may occur because
noise is superimposed on the serial clock signal output by the master device. Unless the strobe control
option is used at this time, the bit shift affects transmission of the next byte. In this case, the master can
detect the bit shift by checking the busy signal during transmission by using the busy control option.
A bit shift is detected by using the busy signal as follows:
The slave outputs the busy signal after the rising of the eighth serial clock during data transmission/reception
(to not keep transmission/reception waiting by the busy signal at this time, make the busy signal inactive
within 2 clocks).
The master samples the busy signal in synchronization with the falling edge of the serial clock if bit 2
(ERRE0) of serial status register 0 (CSIS0) is set to 1. If a bit shift does not occur, all the eight serial clocks
that have been sampled are inactive. If the sampled serial clocks are active, it is assumed that a bit shift has
occurred, error processing is executed (by setting bit 1 (ERRF0) of serial status register 0 (CSIS0) to 1, and
communication is suspended and an interrupt request signal (INTACSI) is output).
Although communication is suspended after completion of 1-byte data communication, slave signal output,
wait due to the busy signal, and wait due to the interval time specified by ADTI0 are not executed.
If ERRE0 = 0, ERRF0 cannot become 1 even if a bit shift occurs.
Figure 17-27 shows the example of the operation timing of the bit shift detection function by the busy signal.
Figure 17-27. Example of Operation Timing of Bit Shift Detection Function by Busy Signal
ACSIIF:
CSIAE0: Bit 7 of serial operation mode specification register 0 (CSIMA0)
ERRF0:
D7
D7 D6 D5 D4 D3 D2 D1 D0
D6 D5 D4 D3 D2 D1 D0
Interrupt request flag
Bit 1 of serial status register 0 (CSIS0)
(When BUSYLV0 = 1)
D7
D7
Busy not detected
D7 D6 D5 D4 D3 D2 D1
D7 D6 D5 D4 D3 D2 D1
CHAPTER 17 SERIAL INTERFACE CSIA0
Bit shift due to noise
D0
D0
Error interrupt request
generated
Error detected
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