UPD78F0513AMC-GAA-AX Renesas Electronics America, UPD78F0513AMC-GAA-AX Datasheet - Page 580

• Manufacturer Part Number: UPD78F0513AMC-GAA-AX
• Description: MCU 8BIT 38PIN SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AMC-GAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
18.5.13 Wakeup function
extension code have been received.
addresses do not match.
addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has
generated a start condition) to a slave device.
wakeup function, and this determines whether interrupt requests are enabled or disabled.
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
During address transmission
Read/write data after address transmission
During extension code transmission
Read/write data after extension code transmission
During data transmission
During ACK transfer period after data transmission
When restart condition is detected during data transfer
When stop condition is detected during data transfer
When data is at low level while attempting to generate a restart
condition
When stop condition is detected while attempting to generate a
restart condition
When data is at low level while attempting to generate a stop
condition
When SCL0 is at low level while attempting to generate a
restart condition
Notes 1. When WTIM0 bit (bit 3 of IIC control register 0 (IICC0)) = 1, an interrupt request occurs at the falling edge of
Remark
The I
This function makes processing more efficient by preventing unnecessary INTIIC0 signal from occurring when
When a start condition is detected, wakeup standby mode is set. This wakeup standby mode is in effect while
However, when a stop condition is detected, bit 4 (SPIE0) of IIC control register 0 (IICC0) is set regardless of the
2
C bus slave function is a function that generates an interrupt request signal (INTIIC0) when a local address and
2. When there is a chance that arbitration will occur, set SPIE0 = 1 for master device operation.
the ninth clock. When WTIM0 = 0 and the extension code’s slave address is received, an interrupt request
occurs at the falling edge of the eighth clock.
SPIE0: Bit 4 of IIC control register 0 (IICC0)
Status During Arbitration
Table 18-5. Status During Arbitration and Interrupt Request Generation Timing
At falling edge of eighth or ninth clock following byte transfer
When stop condition is generated (when SPIE0 = 1)
At falling edge of eighth or ninth clock following byte transfer
When stop condition is generated (when SPIE0 = 1)
At falling edge of eighth or ninth clock following byte transfer
Interrupt Request Generation Timing
CHAPTER 18 SERIAL INTERFACE IIC0
Note 2
Note 2
Note 1
Note 1
Note 1
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