UPD78F0513AMC-GAA-AX Renesas Electronics America, UPD78F0513AMC-GAA-AX Datasheet - Page 975

• Manufacturer Part Number: UPD78F0513AMC-GAA-AX
• Description: MCU 8BIT 38PIN SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AMC-GAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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78K0/Kx2
E.2 Revision History of Preceding Editions
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
3nd Edition
Here is the revision history of the preceding editions. Chapter indicates the chapter of each edition.
Edition
Addition of the conventional-specification products (μPD78F05xx, 78F05xx(A),
78F05xx(A2))
Addition of the (A2) grade products of expanded-specification products
(μPD78F05xxA(A2))
Addition of the 64-pin plastic FBGA (4x4) package
Addition of SM+ tor 78K0
Deletion of QB-78K0MINI, PG-FPL3, and FP-LITE3 (because of discontinued
products)
Addition of Differences Between Conventional-specification Products and
Expanded-specification Products
Modification of Related Documents
Addition of 1.1 Differences Between Conventional-specification Products
(
(
Modification of 1.4 Ordering Information
Modification of 1.8 Outline of Functions
Modification of Table 3-1 Set Values of Internal Memory Size Switching Register
(IMS) (78K0/KB2, and 38-pin products and 44-pin products of the 78K0/KC2)
and Table 3-2 Set Values of Internal Memory Size Switching Register (IMS) and
Internal Expansion RAM Size Switching Register (IXS) (48-pin products of the
78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2)
Addition of description in 3.2.1 (2) Program status word (PSW)
Modification of Notes 2 to 4 in Table 3-8 Special Function Register List (5/5)
Addition of Caution 2 to 5.2.2 Port 1
Modification of Caution in Figure 5-17 Block Diagram of P60 and P61 and Figure
5-18 Block Diagram of P62
Addition of Caution 2 to Figure 6-3. Format of Clock Operation Mode Select
Register (OSCCTL) (78K0/KB2) and Figure 6-4 Format of Clock Operation Mode
Select Register (OSCCTL) (78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2)
Modification of Note 1 in and addition of Note 2 to Figure 6-15 Clock Generator
Operation When Power Supply Voltage Is Turned On (When 1.59 V POC Mode
Is Set (Option Byte: POCMODE = 0))
Addition of Note to Figure 6-17 CPU Clock Status Transition Diagram (When 1.59
V POC Mode Is Set (Option Byte: POCMODE = 0), 78K0/KB2) and Figure 6-18
CPU Clock Status Transition Diagram (When 1.59 V POC Mode Is Set (Option
Byte: POCMODE = 0), 78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2)
Modification of Note 1 in and addition of Note 3 to Figure 7-13 Format of Prescaler
Mode Register 00 (PRM00) and Figure 7-14 Format of Prescaler Mode Register
01 (PRM01)
Modification of description in (f) 16-bit capture/compare register 00n (CR00n) in
Figure 7-46 Example of Register Settings for PPG Output Operation (2/2)
μ
μ
PD78F05xx and 78F05xxD) and Expanded-specification Products
PD78F05xxA and 78F05xxDA)
Description
APPENDIX E REVISION HISTORY
Throughout
INTRODUCTION
CHAPTER 1 OUTLINE
CHAPTER 3 CPU
ARCHITECTURE
CHAPTER 5 PORT
FUNCTIONS
CHAPTER 6 CLOCK
GENERATOR
CHAPTER 7 16-BIT
TIMER/EVENT
COUNTERS 00 AND 01
Chapter
(1/4)
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