UPD78F0513AMC-GAA-AX Renesas Electronics America, UPD78F0513AMC-GAA-AX Datasheet - Page 295

• Manufacturer Part Number: UPD78F0513AMC-GAA-AX
• Description: MCU 8BIT 38PIN SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AMC-GAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
7.4.3 External event counter operation
with the valid edge of the TI00n pin) and bits 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control register 0n
(TMC0n) are set to 11, the valid edge of an external event input is counted, and a match interrupt signal indicating
matching between TM0n and CR00n (INTTM00n) is generated.
event counter in the clear & start mode entered by the TI00n pin valid edge input (when TMC0n3 and TMC0n2 = 10).
following timing.
not detected until it is detected two times in a row. Therefore, a noise with a short pulse width can be eliminated.
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
When bits 1 and 0 (PRM0n1 and PRM0n0) of the prescaler mode register 0n (PRM0n) are set to 11 (for counting up
To input the external event, the TI00n pin is used. Therefore, the timer/event counter cannot be used as an external
The INTTM00n signal is generated with the following timing.
• Timing of generation of INTTM00n signal (second time or later)
However, the first match interrupt immediately after the timer/event counter has started operating is generated with the
• Timing of generation of INTTM00n signal (first time only)
To detect the valid edge, the signal input to the TI00n pin is sampled during the clock cycle of f
Remarks 1. For the setting of I/O pins, see 7.3 (5) Port mode register 0 (PM0).
Remark n = 0:
TI00n pin
= Number of times of detection of valid edge of external event × (Set value of CR00n + 1)
= Number of times of detection of valid edge of external event input × (Set value of CR00n + 2)
2. For how to enable the INTTM00n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS.
n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products
detection
Edge
f
PRS
78K0/KD2 products
78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2,
TMC0n3, TMC0n2
Operable bits
Figure 7-24. Block Diagram of External Event Counter Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
16-bit counter (TM0n)
CR00n register
Clear
Match signal
controller
INTTM00n signal
Output
TO0n output
PRS
. The valid edge is
TO0n pin
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