UPD78F0513AMC-GAA-AX Renesas Electronics America, UPD78F0513AMC-GAA-AX Datasheet - Page 671

• Manufacturer Part Number: UPD78F0513AMC-GAA-AX
• Description: MCU 8BIT 38PIN SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AMC-GAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
Note When the CPU is operating on the subsystem clock and the internal high-speed oscillation clock and high-speed
Remarks 1.
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Item
System clock
CPU
Flash memory
RAM
Port (latch)
16-bit timer/event
counter
8-bit timer/event
counter
8-bit timer
Watch timer
Watchdog timer
Clock output
Buzzer output
A/D converter
Serial interface
Multiplier/divider
Power-on-clear function
Low-voltage detection function
External interrupt
Main system clock
Subsystem clock
f
RL
system clock have been stopped, do not start operation of these functions on the external clock input from
peripheral hardware pins.
2.
HALT Mode Setting
f
f
f
The functions mounted depend on the product. See 1.7 Block Diagram and 1.8 Outline of Functions.
RH
EXCLK
EXCLKS
:
UART0
UART6
CSI10
CSI11
CSIA0
IIC0
: External main system clock,
: External subsystem clock,
Note
f
f
f
f
f
Internal high-speed oscillation clock,
RH
X
EXCLK
XT
EXCLKS
00
01
50
51
H0
H1
Note
Note
Note
Note
Note
Note
Note
Clock supply to the CPU is stopped
Status before HALT mode was set is retained
Operates or stops by external clock input
Operation continues (cannot be stopped)
Operates or stops by external clock input
Status before HALT mode was set is retained
Operation stopped
Status before HALT mode was set is retained
Operable
Operable. Clock supply to watchdog timer stops when “internal low-speed oscillator can be
stopped by software” is set by option byte.
Operable
Operable. However, operation disabled when peripheral hardware clock (f
Operable
When CPU Is Operating on XT1 Clock (f
Table 22-1. Operating Statuses in HALT Mode (2/2)
When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock
f
f
f
X
XT
RL
: X1 clock
: XT1 clock
: Internal low-speed oscillation clock
XT
)
Status before HALT mode was set is retained
Operation continues (cannot be stopped)
CHAPTER 22 STANDBY FUNCTION
When CPU Is Operating on External
Subsystem Clock (f
PRS
) is stopped.
EXCLKS
)
671