UPD78F0513AMC-GAA-AX Renesas Electronics America, UPD78F0513AMC-GAA-AX Datasheet - Page 964

• Manufacturer Part Number: UPD78F0513AMC-GAA-AX
• Description: MCU 8BIT 38PIN SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AMC-GAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Serial
interface
CSIA0
Serial
interface
IIC0
Function
Automatic
transmission/
reception suspension
and restart
Busy control option
Busy & strobe control
option
IIC0: IIC shift register
0
IICC0: IIC control
register 0
IICS0: IIC status
register 0
IICF0: IIC flag register
0
Selection clock setting Determine the transfer clock frequency of I
When
STCEN = 0
When
STCEN = 1
Details of Function
−
If the HALT instruction is executed during automatic transmission/reception,
communication is suspended and the HALT mode is set if during 8-bit data
communication. When the HALT mode is cleared, automatic transmission/reception
is restarted from the suspended point.
When suspending automatic transmission/reception, do not change the operating
mode to 3-wire serial I/O mode while TSF0 = 1.
Busy control cannot be used simultaneously with the interval time control function of
automatic data transfer interval specification register 0 (ADTI0).
When TSF0 is cleared, the SOA0 pin goes low.
Do not use serial interface IIC0 and the multiplier/divider simultaneously, because
various flags corresponding to interrupt request sources are shared among serial
interface IIC0 and the multiplier/divider.
Do not write data to IIC0 during data transfer.
Write or read IIC0 only during the wait period. Accessing IIC0 in a communication
state other than during the wait period is prohibited. When the device serves as the
master, however, IIC0 can be written only once after the communication trigger bit
(STT0) is set to 1.
When communication is reserved, write data to the IIC0 register after the interrupt
triggered by a stop condition is detected.
If the operation of I
SDA0 line is low level, and the digital filter is turned on (DFC0 of the IICCL0 register
= 1), a start condition will be inadvertently detected immediately. In this case, set (1)
the LREL0 bit by using a 1-bit memory manipulation instruction immediately after
enabling operation of I
When bit 3 (TRC0) of the IIC status register 0 (IICS0) is set to 1 (transmission
status), bit 5 (WREL0) of the IICC0 register is set to 1 during the ninth clock and
wait is canceled, after which the TRC0 bit is cleared (reception status) and the
SDAA0 line is set to high impedance. Release the wait performed while the TRC bit
is 1 (transmission status) by writing to the IIC shift register.
If data is read from IICS0 register, a wait cycle is generated. Do not read data from
IICS0 register when the peripheral hardware clock (f
see CHAPTER 36 CAUTIONS FOR WAIT.
Write to STCEN bit only when the operation is stopped (IICE0 = 0).
As the bus release status (IICBSY = 0) is recognized regardless of the actual bus
status when STCEN = 1, when generating the first start condition (STT0 = 1), it is
necessary to verify that no third party communications are in progress in order to
prevent such communications from being destroyed.
Write to IICRSV bit only when the operation is stopped (IICE0 = 0).
CL00 before enabling the operation (by setting bit 7 (IICE0) of IIC control register 0
(IICC0) to 1). To change the transfer clock frequency, clear IICE0 once to 0.
Immediately after I
status (IICBSY (bit 6 of IICF0) = 1) is recognized regardless of the actual bus status.
When changing from a mode in which no stop condition has been detected to a
master device communication mode, first generate a stop condition to release the
bus, then perform master device communication.
When using multiple masters, it is not possible to perform master device
communication when the bus has not been released (when a stop condition has not
been detected).
Use the following sequence for generating a stop condition.
• Set IIC clock selection register 0 (IICCL0).
• Set bit 7 (IICE0) of IIC control register 0 (IICC0) to 1.
• Set bit 0 (SPT0) of IICC0 to 1.
Immediately after I
(IICBSY = 0) is recognized regardless of the actual bus status. To generate the first
start condition (STT0 (bit 1 of IIC control register 0 (IICC0)) = 1), it is necessary to
confirm that the bus has been released, so as to not disturb other communications.
2
2
2
C operation is enabled (IICE0 = 1), the bus communication
C operation is enabled (IICE0 = 1), the bus released status
C is enabled (IICE0 = 1) when the SCL0 line is high level, the
2
C (IICE0 = 1).
Cautions
2
C by using CLX0, SMC0, CL01, and
APPENDIX D LIST OF CAUTIONS
PRS
) is stopped. For details,
p. 544
p. 544
p. 545
p. 547
p. 550
p. 553
p. 553
p. 553
p. 557
p. 560
p. 561
p. 564
p. 564
p. 564
p. 567
p. 584
p. 584
(21/30)
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