UPD78F1211MC-GAA-AX Renesas Electronics America, UPD78F1211MC-GAA-AX Datasheet - Page 329

• Manufacturer Part Number: UPD78F1211MC-GAA-AX
• Description: MCU 16BIT 78K0R/LX3 38-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211MC-GAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 27
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.7.3 Operation as frequency divider(44-pin and 48-pin products of 78K0R/IC3, 78K0R/ID3 and 78K0R/IE3 only.)
result from TOn.
of TDRn when the TIn valid edge is detected. If MDn0 of TMRn = 0 at this time, INTTMn is not output and TOn is not
toggled. If MDn0 of TMRn = 1, INTTMn is output and TOn is toggled.
TCRn loads the value of TDRn again, and continues counting.
period of the TOn output.
The timer array unit can be used as a frequency divider that divides a clock input to the TIn pin and outputs the
The divided clock frequency output from TOn can be calculated by the following expression.
TCRn operates as a down counter in the interval timer mode.
After the channel start trigger bit (TSn) of timer channel start register 0 (TS0) is set to 1, the TCRn loads the value
After that, TCRn counts down at the valid edge of TIn. When TCRn = 0000H, it toggles TOn. At the same time,
If detection of both the edges of TIn is selected, the duty factor error of the input clock affects the divided clock
The period of the TOn output clock includes a sampling error of one period of the operation clock.
TDRn can be rewritten at any time. The new value of TDRn becomes valid during the next count period.
• When rising edge/falling edge is selected:
• When both edges are selected:
Clock period of TOn output = Ideal TOn output clock period ± Operation clock period (error)
Remark
Divided clock frequency = Input clock frequency/{(Set value of TDRn + 1) × 2}
Divided clock frequency ≅ Input clock frequency/(Set value of TDRn + 1)
TIn pin
n = 00, 10, 11 (44-pin and 48-pin products of 78K0R/IC3: n = 10 and 11 )
TSn
detection
Edge
Figure 6-44. Block Diagram of Operation as Frequency Divider
CHAPTER 6 TIMER ARRAY UNIT TAUS
User’s Manual U19678EJ1V1UD
Timer data register n
register n (TCRn)
Timer counter
(TDRn)
controller
Output
TOn pin
327