UPD78F1211MC-GAA-AX Renesas Electronics America, UPD78F1211MC-GAA-AX Datasheet - Page 377

• Manufacturer Part Number: UPD78F1211MC-GAA-AX
• Description: MCU 16BIT 78K0R/LX3 38-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211MC-GAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 27
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(19) TAU option mode register (OPMR)
Address: F0220H
Symbol
OPMR
OPMR sets the operation mode of the inverter control function option unit.
OPMR can be rewritten only if HIE1 and HIE0 of the OPCR register are set to 00B and master channels 00
and 04 of TAUS are stopped (TE00 = 0, TE04 = 0).
OPMR can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Caution There is no TMOFF1 pin in the 78K0R/IB3. Consequently, in the 78K0R/IB3, high
OPM HPS HSM HDM ATS
OPM
HSM
HDM
HPS
15
0
1
0
1
0
1
0
1
6-phase output control mode (TO02 to TO07 become Hi-Z control targets, and Hi-Z control and
cancellation are set by the HDM bit.)
Half-bridge output control mode (when channel 0 and channel 4 are the period registers)
(TO02 and TO03 are set to Hi-Z by the TMOFF0 pin or internal comparator CMP0. TO06 and TO07
are set to Hi-Z by the TMOFF1 pin or internal comparator CMP1. A Hi-Z state is cancelled by the
HSM bit.)
Uses the TMOFF0 and TMOFF1 pins as the Hi-Z control signal.
Uses the internal comparator output signal as the Hi-Z control signal.
A Hi-Z state can be cancelled in synchronization with the period after the inactive edge of an internal
comparator (CMP0/CMP1) or TMOFF0, TMOFF1 is detected.
A Hi-Z state can be cancelled in synchronization with the period after the edge by a software write is
detected.
2-stage overcurrent detection mode
(A Hi-Z state is set when the active edge of internal comparator 0 (CMP0 side) or TMOFF0 is
detected, and the Hi-Z state is cancelled in synchronization with the period after an inactive edge is
detected. Furthermore, a Hi-Z state is set when the active edge of internal comparator 1 (CMP1
side) or TMOFF1 is detected, and the Hi-Z state is cancelled in synchronization with the period after
the edge by a software write is detected.)
Overcurrent/electromotive force detection mode
(A Hi-Z state is set by reversing the internal comparator 0 output or reversing the TMOFF0 active
edge detection, and thus detecting the overcurrent side (high-potential CMP1 or TMOFF1) and the
electromotive force side (low-potential CMP0 or TMOFF0). The Hi-Z state can be cancelled in
synchronization with the period after inactive edge detection of an internal comparator or TMOFF0,
TMOFF1.)
14
After reset: 0000H
Figure 7-10. Format of TAU Option Mode Register (OPMR) (1/2)
impedance cannot be controlled by using the TMOFF1 pin.
13
CHAPTER 7 INVERTER CONTROL FUNCTIONS
12
11
3
R/W
Hi-Z cancellation method selection (when OPM = 1)
Hi-Z cancellation method selection (when OPM = 0)
User’s Manual U19678EJ1V1UD
ATS
10
2
ATS
9
1
Operation mode selection
Hi-Z input pin selection
ATS
8
0
TLS
7
7
TLS
6
6
TLS
5
5
TLS
4
4
TLS
3
3
TLS
2
2
HIS
1
1
HIS
0
0
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