UPD78F1211MC-GAA-AX Renesas Electronics America, UPD78F1211MC-GAA-AX Datasheet - Page 996

• Manufacturer Part Number: UPD78F1211MC-GAA-AX
• Description: MCU 16BIT 78K0R/LX3 38-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211MC-GAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 27
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
994
Instruction
16-bit
operation
Multiply
Group
2.
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When
Mnemonic
ADDW
SUBW
CMPW
MULU
When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no
data access.
When the program memory area is accessed.
fetching an instruction from the internal RAM area, the number of clocks is twice the number of clocks
plus 3, maximum.
register (CKC).
AX, #word
AX, AX
AX, BC
AX, DE
AX, HL
AX, saddrp
AX, !addr16
AX, [HL+byte]
AX, ES:!addr16
AX, ES: [HL+byte]
AX, #word
AX, BC
AX, DE
AX, HL
AX, saddrp
AX, !addr16
AX, [HL+byte]
AX, ES:!addr16
AX, ES: [HL+byte]
AX, #word
AX, BC
AX, DE
AX, HL
AX, saddrp
AX, !addr16
AX, [HL+byte]
AX, ES:!addr16
AX, ES: [HL+byte]
X
Operands
Table 27-5. Operation List (11/17)
CHAPTER 27 INSTRUCTION SET
Bytes
3
1
1
1
1
2
3
3
4
4
3
1
1
1
2
3
3
4
4
3
1
1
1
2
3
3
4
4
1
User’s Manual U19678EJ1V1UD
Note 1 Note 2
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
2
2
1
Clocks
−
−
−
−
−
−
4
4
5
5
−
−
−
−
−
4
4
5
5
−
−
−
−
−
4
4
5
5
−
AX, CY ← AX + word
AX, CY ← AX + AX
AX, CY ← AX + BC
AX, CY ← AX + DE
AX, CY ← AX + HL
AX, CY ← AX + (saddrp)
AX, CY ← AX + (addr16)
AX, CY ← AX + (HL + byte)
AX, CY ← AX + (ES:addr16)
AX, CY ← AX + ((ES:HL) + byte)
AX, CY ← AX − word
AX, CY ← AX − BC
AX, CY ← AX − DE
AX, CY ← AX − HL
AX, CY ← AX − (saddrp)
AX, CY ← AX − (addr16)
AX, CY ← AX − (HL + byte)
AX, CY ← AX − (ES:addr16)
AX, CY ← AX − ((ES:HL) + byte)
AX − word
AX − BC
AX − DE
AX − HL
AX − (saddrp)
AX − (addr16)
AX − (HL + byte)
AX − (ES:addr16)
AX − ((ES:HL) + byte)
AX ← A × X
CPU
) selected by the system clock control
Operation
Z AC CY
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
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×
×
×
×
×
×
Flag
×
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×
×
×
×
×
×
×
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×
×
×
×
×
×
×
×
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×
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×
×
×
×
×
×
×
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