UPD78F1211MC-GAA-AX Renesas Electronics America, UPD78F1211MC-GAA-AX Datasheet - Page 624

• Manufacturer Part Number: UPD78F1211MC-GAA-AX
• Description: MCU 16BIT 78K0R/LX3 38-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211MC-GAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 27
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

622
Address: F0100H, F0101H (SSR00) to F0106H, F0107H (SSR03)
(7) Serial status register 0n (SSR0n)
Symbol
SSR0n
SSR0n register can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of SSR0n register can be set with an 8-bit memory manipulation instruction with SSR0nL.
Reset signal generation clears SSR0n register to 0000H.
Caution If data is written to the SDR0n register when BFF0n = 1, the transmit/receive data stored in
Remark
SSR0n register is a register that indicates the communication status and error occurrence status of channel n.
The errors indicated by this register are a framing error, parity error, and overrun error.
<Clear conditions>
• Communication ends.
<Set condition>
• Communication starts.
<Clear conditions>
• Transferring transmit data from the SDR0n register to the shift register ends during transmission.
• Reading receive data from the SDR0n register ends during reception.
• The ST0n bit of the ST0 register is set to 1 (communication is stopped) or the SS0n bit of the SS0 register is set to
<Set conditions>
• Transmit data is written to the SDR0n register while the TXE0n bit of the SCR0n register is set to 1 (transmission
• Receive data is stored in the SDR0n register while the RXE0n bit of the SCR0n register is set to 1 (reception or
• A reception error occurs.
• The ST0n bit of the ST0 register is set to 1 (communication is stopped) or the SS0n bit of the SS0 register is set
TSF
BFF
0n
0n
15
1 (communication is enabled).
or transmission and reception mode in each communication mode).
transmission and reception mode in each communication mode).
0
1
0
1
0
to 1 (communication is suspended).
the register is discarded and an overrun error (OVE0n = 1) is detected.
n: Channel number (n = 0 to 3)
Communication is stopped or suspended.
Communication is in progress.
Valid data is not stored in the SDR0n register.
Valid data is stored in the SDR0n register.
14
0
Figure 13-10. Format of Serial Status Register 0n (SSR0n) (1/2)
13
0
12
0
CHAPTER 13 SERIAL ARRAY UNIT
11
0
User’s Manual U19678EJ1V1UD
Communication status indication flag of channel n
Buffer register status indication flag of channel n
10
0
9
0
8
0
After reset: 0000H
7
0
TSF
0n
6
BFF
0n
5
R
4
0
3
0
FEF
0n
2
PEF
0n
1
OVF
0n
0