UPD78F1211MC-GAA-AX Renesas Electronics America, UPD78F1211MC-GAA-AX Datasheet - Page 337

• Manufacturer Part Number: UPD78F1211MC-GAA-AX
• Description: MCU 16BIT 78K0R/LX3 38-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211MC-GAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 27
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.7.5 Operation as input signal high-/low-level width measurement
level width/low-level width) of TIn can be measured. The signal width of TIn can be calculated by the following
expression.
TIn pin start edge detection wait status is set.
counter counts up from 0000H in synchronization with the count clock. When the valid capture edge (falling edge of
TIn when the high-level width is to be measured) is detected later, the count value is transferred to TDRn and, at the
same time, INTTMn is output. If the counter overflows at this time, the OVF bit of the TSRn register is set to 1. If the
counter does not overflow, the OVF bit is cleared. TCRn stops at the value “value transferred to TDRn + 1”, and the
TIn pin start edge detection wait status is set. After that, the above operation is repeated.
depending on whether the counter overflows during the measurement period. Therefore, the overflow status of the
captured value can be checked.
bit of the TSRn register is set to 1.
OVF bit, if two or more overflows occur.
and CISn0 bits of the TMRn register.
1.
By starting counting at one edge of TIn and capturing the number of counts at another edge, the signal width (high-
TCRn operates as an up counter in the capture & one-count mode.
When the channel start trigger (TSn) of the timer channel start register 0 (TS0) is set to 1, TEn is set to 1 and the
When the TIn start edge (rising edge of TIn pin input when the high-level width is to be measured) is detected, the
At the same time that the count value is captured to the TDRn register, the OVF bit of the TSRn register is updated
If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVF
Whether the high-level width or low-level width of the TIn pin is to be measured can be selected by using the CISn1
Because this function is used to measure the signal width of the TIn pin input, TSn cannot be set to 1 while TEn is
CISn1, CISn0 of TMRn = 10B: Low-level width is measured.
CISn1, CISn0 of TMRn = 11B: High-level width is measured.
Signal width of TIn input = Period of count clock × ((10000H × TSRn: OVF) + (Capture value of TDRn + 1))
Remark
Caution When using a channel to implement the LIN-bus, set bit 1 (ISC1) of the input switch control
Caution The TIn pin input is sampled using the operating clock selected with the CKSn bit of the
register (ISC) to 1. RxD0 signal will be input to the channel 7.
Also, when RxD0 functions alternately as a timer input pin, the corresponding timer input pin
channels can also be used for the LIN-bus function. The timer channels in each version of
the 78K0R/Ix3 that can be used for the LIN-bus function in addition to timer channel 7 are
shown below.
description.
TMRn register, so an error equivalent to one operation clock occurs.
n = 00 to 11 (78K0R/IB3: n = 02 to 07 and 09)
When using a channel to implement the LIN-bus, Read “TIn” as “RxD0” in the following
78K0R/IB3 (P11/RxD0/TI03/TO03)
38-pin products of 78K0R/IC3 (P72/INTP6/RxD0)
44-pin and 48-pin products of 78K0R/IC3, 78K0R/ID3,
78K0R/IE3 (P74/RxD0/TI10/SI00)
However, the correct value of high/low level width cannot be measured for the
CHAPTER 6 TIMER ARRAY UNIT TAUS
User’s Manual U19678EJ1V1UD
: Channel 3 of TAUS
: None
: Chanel 10 of TAUS
335