UPD78F1211MC-GAA-AX Renesas Electronics America, UPD78F1211MC-GAA-AX Datasheet - Page 793

• Manufacturer Part Number: UPD78F1211MC-GAA-AX
• Description: MCU 16BIT 78K0R/LX3 38-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211MC-GAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 27
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.5.12 Arbitration
1), communication among the master devices is performed as the number of clocks are adjusted until the data differs.
This kind of operation is called arbitration.
is set (1) via the timing by which the arbitration loss occurred, and the SCL0 and SDA0 lines are both set to high
impedance, which releases the bus.
stop condition is detected, etc.) and the ALD = 1 setting that has been made by software.
control.
Transfer lines
When several master devices simultaneously generate a start condition (when STT is set to 1 before STD is set to
When one of the master devices loses in arbitration, an arbitration loss flag (ALD) in the IICA status register (IICS)
The arbitration loss is detected based on the timing of the next interrupt request (the eighth or ninth clock, when a
For details of interrupt request timing, see 14.5.8 Interrupt request (INTIICA) generation timing and wait
Remark
Master 1
Master 2
SDA0
SDA0
SDA0
SCL0
SCL0
SCL0
STD:
STT:
Bit 1 of IICA status register (IICS)
Bit 1 of IICA control register 0 (IICCTL0)
Figure 14-21. Arbitration Timing Example
CHAPTER 14 SERIAL INTERFACE IICA
User’s Manual U19678EJ1V1UD
Master 1 loses arbitration
Hi-Z
Hi-Z
791