UPD78F1211MC-GAA-AX Renesas Electronics America, UPD78F1211MC-GAA-AX Datasheet - Page 415

• Manufacturer Part Number: UPD78F1211MC-GAA-AX
• Description: MCU 16BIT 78K0R/LX3 38-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211MC-GAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 27
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.5.5 Operation as triangular wave PWM output function with dead time
channels 4 to 7 in combination to output a triangular wave PWM waveform (with dead time).
7. Slave channels 1 and 5 can be operated in any operation mode.
following equations.
positive-phase wave will be shortened by the amount of dead time, and the output width of a reverse- phase wave will
be extended by the amount of dead time. The linearity of output transition will be lost in the neighborhood of 0% and
100% outputs due to the errors.
value of TDRn again at the same timing. Similar operation is continued hereafter.
status of the slave channel and the second period as an up status of the slave channel.
set, because up and down statuses are output.
an up status.
The triangular wave modulation PWM output function with dead time uses four channels of channels 0 to 3 or
It outputs riangular wave modulation PWM with dead times from slave channels 2 and 3, and slave channels 6 and
The output pulse cycle, positive-phase active width, and reverse-phase active width can be calculated by using the
Errors will be included in the output waveforms when the dead time function is used. The output width of a
At the master channel, channels 0 and 4 are used.
TCRn operates as a down counter in the interval timer mode.
TCRn loads the value of TDRn at the first count clock, after the channel start trigger bit (TSn) is set to 1.
Afterward, TCRn counts down along with the count clock.
When TCRn has become 0000H, INTTMn is output and TOn is toggled upon the next count clock. TCRn loads the
A carrier period is generated in two periods of the master channel count.
The count operation of the slave channel is controlled by defining the first period of the master channel as a down
TOn of the master channel outputs up and down statuses.
TOn of the TO0 register must be manipulated while TOEn of the TOE0 register is 0 and the default level must be
TOn of the TO0 register is set to 1 when MDn0 of the TMRn register is 0, and TOn is set to 0 when MDn0 is 1.
By setting the default level, a high level is output from TO00 during a down status and a low level is output during
Remark n = 00, 04
Pulse period (down/up) = {Set value of TDRn (master) + 1} × 2 × Count clock period
positive-phase active width = {{{Set value of TDRn (master) + 1} − {Set value of TDRp (slave p) }} × 2 −
{Set value of TDRq (slave q) + 1}} × Count clock period
reverse-phase active width = {{{Set value of TDRn (master) + 1} − {Set value of TDRp (slave p) }} × 2 +
{Set value of TDRq (slave q) + 1}} × Count clock period
0% output: Set value of TDRp (slave p) ≥ Set value of TDRn (master) + 1
100% output: Set value of TDRp (slave p) = 0000H
p = 02, 06
q = 03, 07
CHAPTER 7 INVERTER CONTROL FUNCTIONS
User’s Manual U19678EJ1V1UD
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