UPD78F1211MC-GAA-AX Renesas Electronics America, UPD78F1211MC-GAA-AX Datasheet - Page 422

• Manufacturer Part Number: UPD78F1211MC-GAA-AX
• Description: MCU 16BIT 78K0R/LX3 38-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211MC-GAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 27
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Remark n = 00, 04 p = 02, 06 q = 03, 07
420
Figure 7-38. Operation Procedure When Triangular Wave PWM Output Function with Dead Time Is Used (1/2)
TAUS
default
setting
Channel
default
setting
Operation
start
During
operation
Sets the TAU0EN and TAUOPEN bits of the PER2
register to 1.
Sets the TPS0 register.
Sets the TMRn, TMRp, and TMRq registers of four
channels to be used (determines operation mode of
channels).
An interval (period) value is set to the TDRn register of
the master channel, a duty factor is set to the TDRp
register of slave channels 2, 6, and a dead time width is
set to the TDRq register of slave channels 3, 7.
Sets slave channels.
Sets the TOn, TOp, and TOq bits, and determines
default levels of TOn, TOp, and TOq.
Sets the TOEn, TOEp, and TOEq bits to 1 and enables
operation of TOn, TOp, and TOq.
Clears the port register and port mode register to 0.
Sets the TOEm (master), and TOEp and TOEq (slaves)
bits to 1 (only when operation is resumed).
The TSn (master), and TSp and TSq (slaves) bits of the
TS0 register are set to 1 at the same time.
The set value of the TDRn (master) register must be
changed during an up status period of slave channels 2,
6.
The set values of the TDRp and TDRq (slaves) register
can be changed.
The TCRn, TCRp, and TCRq registers can always be
read.
The TSRp (slave) register can always be read.
Determines the clock frequencies of CK00 and CK01.
The TOMp and TOMq bits of the TOM0 register, and
the TOTp and TOTq bits of the TOT0 register are set
to 1 (triangular wave PWM generation).
Sets the TOLp and TOLq bits, and determines the
active levels of the TOp and TOq outputs.
Sets the TDEp and TDEq bits to 1 (dead time control
enable).
The TSn, TSp, and TSq bits automatically return to 0
because they are trigger bits.
Software Operation
CHAPTER 7 INVERTER CONTROL FUNCTIONS
User’s Manual U19678EJ1V1UD
Power-off status
Power-on status. Each channel stops operating.
Channel stops operating.
(Clock is supplied and some power is consumed.)
The TO00, TOp, and TOq pins go into Hi-Z output states.
The TOn, TOp, and TOq default setting levels are output
when the port mode register is in output mode and the port
register is 0.
TOn, TOp, and TOq do not change because channels stop
operating.
The TOn, TOp, and TOq pins output the TOn, TOp, and TOq
set levels.
TEn = 1, TEp = 1, TEq = 1
At the master channel, a period is generated and count
operation of slave channels are controlled. A PWM duty is
generated at slave channels 2, 6, and dead time is
generated at slave channels 3, 7.
Triangular wave PWM waveforms with dead times are output
from the TOp and TOq pins by a combined operation of
slave channels 2, 6 and slave channels 3, 7.
(Clock supply is stopped and writing to each register is
disabled.)
(Clock supply is started and writing to each register is
enabled.)
When the master channel and slave channels 2, 6 start
counting, and when the MDn0 bit of the TMRn register is
set to 1, INTTMn is generated. Slave channels 3, 7 wait
until slave channels 2, 6 detect INTTMp.
Hardware Status