MCF5307FT90B Freescale Semiconductor, MCF5307FT90B Datasheet - Page 110
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MCF5307FT90B
Manufacturer Part Number
MCF5307FT90B
Description
IC MPU 32BIT COLDF 90MHZ 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets
1.MCF5307AI66B.pdf
(484 pages)
2.MCF5307AI66B.pdf
(16 pages)
3.MCF5307AI66B.pdf
(2 pages)
Specifications of MCF5307FT90B
Core Processor
Coldfire V3
Core Size
32-Bit
Speed
90MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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Cache Operation
be deallocated and replaced. First the cache controller looks for an invalid line, with way 0
the highest priority. If all lines have valid data, a 2-bit replacement counter is used to choose
the way. After a line is allocated, the pointer increments to point to the next way.
Cache lines from ways 0 and 1 can be protected from deallocation by enabling half-cache
locking. If CACR[HLCK] = 1, the replacement pointer is restricted to way 2 or 3.
As part of deallocation, a valid, unmodified cache line is invalidated. It is consistent with
system memory, so memory does not need to be updated. To deallocate a modified cache
line, data is placed in a push buffer (for an external cache line push) before being
invalidated. After invalidation, the new entry can replace it. The old cache line may be
written after the new line is read.
When a cache line is selected to host a new cache entry, the following three things happen:
Read cycles that miss in the cache allocate normally as previously described.
Write cycles that miss in the cache do not allocate on a cacheable write-through region, but
do allocate for addresses in a cacheable copyback region.
A copyback byte, word, longword, or line write miss causes the following:
Note the following:
Write accesses designated as cache-inhibited by the CACR or ACR bypass the cache and
perform a corresponding external write.
4-12
1. The new address tag bits A[31:11] are written to the tag.
2. The cache line is updated with the new memory data.
3. The cache line status changes to a valid state (V = 1).
1. The cache initiates a line fill or flush.
2. Space is allocated for a new line.
3. V and M are both set to indicate valid and modified.
4. Data is written in the allocated space. No write to memory occurs.
• Read hits cannot change the status bits and no deallocation or replacement occurs;
• If the cache hits on a write access, data is written to the appropriate portion of the
• Misaligned accesses are broken into at least two cache accesses.
• Validity is provided only on a line basis. Unless a whole line is loaded on a cache
the data or instructions are read from the cache.
accessed cache line. Write hits in cacheable, write-through regions generate an
external write cycle and the cache line is marked valid, but is never marked modified.
Write hits in cacheable copyback regions do not perform an external write cycle; the
cache line is marked valid and modified (V = 1 and M = 1).
miss, the cache controller does not validate data in the cache line.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
MCF5307 User’s Manual
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