MCF5307FT90B Freescale Semiconductor, MCF5307FT90B Datasheet - Page 405

• Manufacturer Part Number: MCF5307FT90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307FT90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Instruction words and extension words (opcodes) must reside on word boundaries.
Attempting to prefetch a misaligned instruction word causes an address error exception.
The MCF5307 converts misaligned, cache-inhibited operand accesses to multiple aligned
accesses. Figure 18-21 shows the transfer of a longword operand from a byte address to a
32-bit port. In this example, SIZ[1:0] specify a byte transfer and a byte offset of 0x1. The
slave device supplies the byte and acknowledges the data transfer. When the MCF5307
starts the second cycle, SIZ[1:0] specify a word transfer with a byte offset of 0x2. The next
two bytes are transferred in this cycle. In the third cycle, byte 3 is transferred. The byte
offset is now 0x0, the port supplies the final byte, and the operation is complete.
If an operand is cacheable and is misaligned across a cache-line boundary, both lines are
loaded into the cache. The example in Figure 18-22 differs from the one in Figure 18-21 in
that the operand is word-sized and the transfer takes only two bus cycles.
18.6 Bus Errors
The MCF5307 has no bus monitor. If the auto-acknowledge feature is not enabled for the
address that generates the error, the bus cycle can be terminated by asserting TA or by using
the software watchdog timer. If it is required that the MCF5307 handle a bus error
differently, an interrupt handler can be invoked by asserting an interrupt to the core along
with TA when the bus error occurs.
18.7 Interrupt Exceptions
A peripheral device uses the interrupt-request signals (IRQx) to signal the core to take an
interrupt exception when it needs the MCF5307 or is ready to send information to it. The
interrupt transfers control to an appropriate routine.
Figure 18-21. Example of a Misaligned Longword Transfer (32-Bit Port)
Transfer 1
Transfer 2
Transfer 3
Transfer 1
Transfer 2
Figure 18-22. Example of a Misaligned Word Transfer (32-Bit Port)
External masters using internal MCF5307 chip selects and
default memory control signals must initiate aligned transfers.
31
31
Byte 3
Byte 0
Freescale Semiconductor, Inc.
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For More Information On This Product,
24 23
24 23
Chapter 18. Bus Operation
Go to: www.freescale.com
Byte 0
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NOTE:
16 15
16 15
Byte 1
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8 7
8 7
Byte 2
Byte 0
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0
0
A[2:0]
A[2:0]
001
010
100
001
100
Bus Errors
18-17