MCF5307FT90B Freescale Semiconductor, MCF5307FT90B Datasheet - Page 79
MCF5307FT90B
Manufacturer Part Number
MCF5307FT90B
Description
IC MPU 32BIT COLDF 90MHZ 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets
1.MCF5307AI66B.pdf
(484 pages)
2.MCF5307AI66B.pdf
(16 pages)
3.MCF5307AI66B.pdf
(2 pages)
Specifications of MCF5307FT90B
Core Processor
Coldfire V3
Core Size
32-Bit
Speed
90MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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MOVEM
MOVEQ
MSAC
MSACL
MULS
MULU
NEG
NEGX
NOP
NOT
OR
ORI
PEA
PULSE
REMS
REMU
RTS
Scc
SUB
SUBA
SUBI
SUBQ
SUBX
SWAP
TRAP
TRAPF
Instruction
#<list>,<ea-2>x
<ea-2>y,#<list>
#<data>,Dx
Ry,RxSF
Ry,RxSF,<ea-1>y,Rw
<ea>y,Dx
<ea>y,Dx
Dx
Dx
none
Dx
<ea>y,Dx
Dy,<ea>x
#<data>,Dx
<ea-3>y
none
<ea-1>,Dx
<ea-1>,Dx
none
Dx
<ea>y,Dx
Dy,<ea>x
<ea>y,Ax
#<data>,Dx
#<data>,<ea>x
Dy,Dx
Dx
#<vector>
None
#<data>
Operand Syntax
Table 2-7. User-Mode Instruction Set Summary (Continued)
Freescale Semiconductor, Inc.
For More Information On This Product,
.L
.L
.B → .L
.L - (.W × .W) → .L
.L - (.L × .L) → .L
.L - (.W × .W) → .L, .L
.L - (.L × .L) → .L, .L
.W X .W → .L
.L X .L → .L
.W X .W → .L
.L X .L → .L
.L
.L
Unsized
.L
.L
.L
.L
Unsized
.L
.L
Unsized
.B
.L
.L
.L
.L
.L
.L
.W
Unsized
Unsized
.W
.L
Operand Size
Chapter 2. ColdFire Core
Go to: www.freescale.com
Listed registers → destination
Source → listed registers
Sign-extended immediate data → destination
ACC – (Ry × Rx){<< 1 | >> 1} → ACC
ACC – (Ry × Rx){<< 1 | >> 1} → ACC;
(<ea-1>y{&MASK}) → Rw
Source × destination → destination
Signed operation
Source × destination → destination
Unsigned operation
0 – destination → destination
0 – destination – X → destination
Synchronize pipelines; PC + 2 → PC
~ Destination → destination
Source | destination → destination
Immediate data | destination → destination
SP – 4 → SP; Address of <ea> → (SP)
Set PST= 0x4
Dx/<ea>y → Dw {32-bit remainder}
Signed operation
Dx/<ea>y → Dw {32-bit remainder}
Unsigned operation
(SP) → PC; SP + 4 → SP
If condition true, then 1s destination;
Else 0s → destination
Destination – source → destination
Destination – source → destination
Destination – immediate data → destination
Destination – immediate data → destination
Destination – source – X → destination
MSW of Dx ←→ LSW of Dx
SP – 4 → SP;PC → (SP);
SP – 2 → SP;SR → (SP);
SP – 2 → SP; format → (SP);
Vector address → PC
PC + 2 → PC
PC + 4 → PC
PC + 6 → PC
Operation
Instruction Set Summary
2-39
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