MCF5307FT90B Freescale Semiconductor, MCF5307FT90B Datasheet - Page 117

no-image

MCF5307FT90B

Manufacturer Part Number
MCF5307FT90B
Description
IC MPU 32BIT COLDF 90MHZ 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets

Specifications of MCF5307FT90B

Core Processor
Coldfire V3
Core Size
32-Bit
Speed
90MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCF5307FT90B
Manufacturer:
ON
Quantity:
51
Part Number:
MCF5307FT90B
Manufacturer:
MOT
Quantity:
5 510
Part Number:
MCF5307FT90B
Quantity:
5 510
Part Number:
MCF5307FT90B
Manufacturer:
MOTOLOLA
Quantity:
650
Part Number:
MCF5307FT90B
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCF5307FT90B
Manufacturer:
FREESCALE
Quantity:
20 000
Freescale Semiconductor, Inc.
Cache Operation
another cache fill is required (for example, cache miss to process) during the continued
instruction execution by the processor pipeline, the pipeline stalls until the push and store
buffers are empty, then generate the required external bus transaction.
Supervisor instructions, the NOP instruction, and exception processing synchronize the
processor core and guarantee the push and store buffers are empty before proceeding. Note
that the NOP instruction should be used only to synchronize the pipeline. The preferred
no-operation function is the TPF instruction.
4.9.6 Cache Locking
Ways 0 and 1 of the cache can be locked by setting CACR[HLCK]. If the cache is locked,
cache lines in ways 0 and 1 are not subject to being deallocated by normal cache operations.
As Figure 4-7 (B and C) shows, the algorithm for updating the cache and for identifying
cache lines to be deallocated is otherwise unchanged. If ways 2 and 3 are entirely invalid,
cacheable accesses are first allocated in way 2. Way 3 is not used until the location in way 2
is occupied.
Ways 0 and 1 are still updated on write hits (D in Figure 4-7) and may be pushed or cleared
only explicitly by using specific cache push/invalidate instructions. However, new cache
lines cannot be allocated in ways 0 and 1.
Chapter 4. Local Memory
4-19
For More Information On This Product,
Go to: www.freescale.com

Related parts for MCF5307FT90B