MCF5307FT90B Freescale Semiconductor, MCF5307FT90B Datasheet - Page 12

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MCF5307FT90B

Manufacturer Part Number
MCF5307FT90B
Description
IC MPU 32BIT COLDF 90MHZ 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets

Specifications of MCF5307FT90B

Core Processor
Coldfire V3
Core Size
32-Bit
Speed
90MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

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Paragraph
Number
11.3.3.2
11.3.3.3
11.3.3.4
11.3.3.5
11.4
11.4.1
11.4.2
11.4.3
11.4.3.1
11.4.3.2
11.4.3.3
11.4.4
11.4.4.1
11.4.4.2
11.4.4.3
11.4.4.4
11.4.4.5
11.4.4.6
11.4.5
11.4.5.1
11.5
11.5.1
11.5.2
11.5.3
11.5.4
11.5.5
11.5.6
12.1
12.1.1
12.2
12.3
12.4
12.4.1
12.4.2
xii
Synchronous Operation................................................................................... 11-16
SDRAM Example ........................................................................................... 11-34
Overview........................................................................................................... 12-1
DMA Signal Description .................................................................................. 12-2
DMA Transfer Overview.................................................................................. 12-3
DMA Controller Module Programming Model................................................ 12-4
DRAM Controller Signals in Synchronous Mode...................................... 11-17
Using Edge Select (EDGESEL) ................................................................. 11-18
Synchronous Register Set ........................................................................... 11-19
General Synchronous Operation Guidelines............................................... 11-23
Initialization Sequence................................................................................ 11-33
SDRAM Interface Configuration................................................................ 11-35
DCR Initialization....................................................................................... 11-35
DACR Initialization.................................................................................... 11-35
DMR Initialization...................................................................................... 11-37
Mode Register Initialization ....................................................................... 11-38
Initialization Code....................................................................................... 11-39
DMA Module Features ................................................................................. 12-2
Source Address Registers (SAR0–SAR3) .................................................... 12-6
Destination Address Registers (DAR0–DAR3) ........................................... 12-7
Burst Page-Mode Operation ................................................................... 11-12
Continuous Page Mode........................................................................... 11-13
Extended Data Out (EDO) Operation..................................................... 11-15
Refresh Operation ................................................................................... 11-16
DRAM Control Register (DCR) in Synchronous Mode.......................... 11-19
DRAM Address and Control Registers (DACR0/DACR1)
DRAM Controller Mask Registers (DMR0/DMR1) .............................. 11-22
Address Multiplexing ............................................................................. 11-23
Interfacing Example................................................................................ 11-27
Burst Page Mode..................................................................................... 11-27
Continuous Page Mode........................................................................... 11-29
Auto-Refresh Operation.......................................................................... 11-31
Self-Refresh Operation ........................................................................... 11-32
Mode Register Settings........................................................................... 11-33
in Synchronous Mode ......................................................................... 11-20
Freescale Semiconductor, Inc.
For More Information On This Product,
DMA Controller Module
Go to: www.freescale.com
Peripheral Module
MCF5307 User’s Manual
CONTENTS
Chapter 12
Part III
Title
Number
Page

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