MCF5307FT90B Freescale Semiconductor, MCF5307FT90B Datasheet - Page 461

• Manufacturer Part Number: MCF5307FT90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307FT90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

1
MBAR
Offset
MBAR
Offset
0x08C
0x09C
0x0AC
Addresses not assigned to a register and undefined register bits are reserved for expansion. Write accesses to
these reserved address spaces and reserved register bits have no effect.
MBAR
Offset
0x10C
0x080
0x084
0x088
0x090
0x094
0x098
0x0A0
0x0A4
0x0A8
0x0B0
0x0B4
0x0B8
0x100
0x104
0x108
0x110
0x114
Chip-select address register—bank 0 (CSAR0)
Chip-select address register—bank 1 (CSAR1)
Chip-select address register—bank 2 (CSAR2)
Chip-select address register—bank 3 (CSAR3)
Chip-select address register—bank 4 (CSAR4)
DRAM control register (DCR) [p. 11-3]
[31:24]
[31:24]
[31:24]
Table A-3. Chip-Select Registers (Continued)
Freescale Semiconductor, Inc.
Table A-4. DRAM Controller Registers
Reserved
Reserved
Reserved
Reserved
Reserved
For More Information On This Product,
[p. 10-6]
[p. 10-6]
[p. 10-6]
[p. 10-6]
[p. 10-6]
DRAM address and control register 0 (DACR0) [p. 11-3]
DRAM address and control register 1 (DACR1) [p. 11-3]
Appendix A. List of Memory Maps
Chip-select mask register—bank 0 (CSMR0) [p. 10-6]
Chip-select mask register—bank 1 (CSMR1) [p. 10-6]
Chip-select mask register—bank 2 (CSMR2) [p. 10-6]
Chip-select mask register—bank 3 (CSMR3) [p. 10-6]
Chip-select mask register—bank 4 (CSMR4) [p. 10-6]
DRAM mask register block 0 (DMR0) [p. 11-3]
DRAM mask register block 1 (DMR1) [p. 11-3]
1
1
1
1
1
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[23:16]
[23:16]
[23:16]
Reserved
Chip-select control register—bank 0 (CSCR0)
Chip-select control register—bank 1 (CSCR1)
Chip-select control register—bank 2 (CSCR2)
Chip-select control register—bank 3 (CSCR3)
Chip-select control register—bank 4 (CSCR4)
[15:8]
[15:8]
[15:8]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
[p. 10-8]
[p. 10-8]
[p. 10-8]
[p. 10-8]
[p. 10-8]
1
1
1
1
1
[7:0]
[7:0]
[7:0]
A-3