MCF5307FT90B Freescale Semiconductor, MCF5307FT90B Datasheet - Page 23
MCF5307FT90B
Manufacturer Part Number
MCF5307FT90B
Description
IC MPU 32BIT COLDF 90MHZ 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets
1.MCF5307AI66B.pdf
(484 pages)
2.MCF5307AI66B.pdf
(16 pages)
3.MCF5307AI66B.pdf
(2 pages)
Specifications of MCF5307FT90B
Core Processor
Coldfire V3
Core Size
32-Bit
Speed
90MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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Figure
Number
14-10
14-11
14-12
14-13
14-14
14-15
14-17
14-16
14-18
14-19
14-20
14-21
14-22
14-23
14-24
14-25
14-26
14-27
15-1
15-2
15-3
16-1
16-2
16-3
17-1
18-1
18-2
18-3
18-4
18-5
18-6
18-7
18-8
18-9
18-10
18-11
18-12
18-13
18-14
18-15
18-16
18-17
18-18
UART Auxiliary Control Register (UACRn) ........................................................... 14-13
UART Interrupt Status/Mask Registers (UISRn/UIMRn)........................................ 14-13
UART Divider Upper Register (UDUn)................................................................... 14-14
UART Divider Lower Register (UDLn)................................................................... 14-14
UART Interrupt Vector Register (UIVRn) ............................................................... 14-15
UART Input Port Register (UIPn) ............................................................................ 14-15
UART Block Diagram Showing External and Internal Interface Signals ................ 14-16
UART Output Port Command Register (UOP1/UOP0) ........................................... 14-16
UART/RS-232 Interface ........................................................................................... 14-17
Clocking Source Diagram......................................................................................... 14-18
Transmitter and Receiver Functional Diagram......................................................... 14-20
Transmitter Timing Diagram .................................................................................... 14-22
Receiver Timing........................................................................................................ 14-23
Automatic Echo ........................................................................................................ 14-25
Local Loop-Back ...................................................................................................... 14-26
Remote Loop-Back ................................................................................................... 14-26
Multidrop Mode Timing Diagram ............................................................................ 14-27
UART Mode Programming Flowchart ..................................................................... 14-30
Parallel Port Pin Assignment Register (PAR) ............................................................ 15-1
Port A Data Direction Register (PADDR).................................................................. 15-2
Port A Data Register (PADAT) .................................................................................. 15-3
Mechanical Diagram................................................................................................... 16-9
MCF5307 Case Drawing (General View) ................................................................ 16-10
Case Drawing (Details)............................................................................................. 16-11
MCF5307 Block Diagram with Signal Interfaces ...................................................... 17-2
Signal Relationship to BCLKO for Non-DRAM Access ........................................... 18-2
Connections for External Memory Port Sizes ............................................................ 18-4
Chip-Select Module Output Timing Diagram ............................................................ 18-4
Data Transfer State Transition Diagram ..................................................................... 18-6
Read Cycle Flowchart................................................................................................. 18-7
Basic Read Bus Cycle................................................................................................. 18-8
Write Cycle Flowchart................................................................................................ 18-9
Basic Write Bus Cycle ................................................................................................ 18-9
Read Cycle with Fast Termination ........................................................................... 18-10
Write Cycle with Fast Termination........................................................................... 18-10
Back-to-Back Bus Cycles ......................................................................................... 18-11
Line Read Burst (2-1-1-1), External Termination .................................................... 18-12
Line Read Burst (2-1-1-1), Internal Termination ..................................................... 18-13
Line Read Burst (3-2-2-2), External Termination .................................................... 18-13
Line Read Burst-Inhibited, Fast, External Termination............................................ 18-14
Line Write Burst (2-1-1-1), Internal/External Termination...................................... 18-14
Line Write Burst (3-2-2-2) with One Wait State, Internal Termination ................... 18-15
Line Write Burst-Inhibited, Internal Termination .................................................... 18-15
Freescale Semiconductor, Inc.
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