MCF5307FT90B Freescale Semiconductor, MCF5307FT90B Datasheet - Page 14

• Manufacturer Part Number: MCF5307FT90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307FT90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Paragraph
Number
14.3.4
14.3.5
14.3.6
14.3.7
14.3.8
14.3.9
14.3.10
14.3.11
14.3.12
14.3.13
14.3.14
14.4
14.5
14.5.1
14.5.1.1
14.5.1.2
14.5.1.2.1
14.5.1.2.2
14.5.2
14.5.2.1
14.5.2.2
14.5.2.3
14.5.3
14.5.3.1
14.5.3.2
14.5.3.3
14.5.4
14.5.5
14.5.5.1
14.5.5.2
14.5.5.3
14.5.6
14.5.6.1
15.1
15.1.1
15.1.2
15.1.3
15.1.4
xiv
UART Module Signal Definitions .................................................................. 14-16
Operation......................................................................................................... 14-18
Parallel Port Operation...................................................................................... 15-1
UART Clock-Select Registers (UCSRn)...................................................... 14-8
UART Command Registers (UCRn) ............................................................ 14-9
UART Receiver Buffers (URBn) ............................................................... 14-11
UART Transmitter Buffers (UTBn) ........................................................... 14-11
UART Input Port Change Registers (UIPCRn).......................................... 14-12
UART Auxiliary Control Register (UACRn)............................................. 14-12
UART Interrupt Status/Mask Registers (UISRn/UIMRn).......................... 14-13
UART Divider Upper/Lower Registers (UDUn/UDLn) ............................ 14-14
UART Interrupt Vector Register (UIVRn)................................................. 14-15
UART Input Port Register (UIPn) .............................................................. 14-15
UART Output Port Command Registers (UOP1n/UOP0n) ....................... 14-15
Transmitter/Receiver Clock Source............................................................ 14-18
Transmitter and Receiver Operating Modes............................................... 14-19
Looping Modes ........................................................................................... 14-25
Multidrop Mode.......................................................................................... 14-26
Bus Operation ............................................................................................. 14-28
Programming .............................................................................................. 14-28
Pin Assignment Register (PAR) ................................................................... 15-1
Port A Data Direction Register (PADDR).................................................... 15-2
Port A Data Register (PADAT) .................................................................... 15-2
Code Example............................................................................................... 15-3
Programmable Divider............................................................................ 14-18
Calculating Baud Rates........................................................................... 14-19
Transmitting ........................................................................................... 14-21
Receiver .................................................................................................. 14-22
FIFO Stack ............................................................................................. 14-24
Automatic Echo Mode ............................................................................ 14-25
Local Loop-Back Mode .......................................................................... 14-25
Remote Loop-Back Mode....................................................................... 14-26
Read Cycles ............................................................................................ 14-28
Write Cycles ........................................................................................... 14-28
Interrupt Acknowledge Cycles ............................................................... 14-28
UART Module Initialization Sequence .................................................. 14-29
BCLKO Baud Rates ........................................................................... 14-19
External Clock .................................................................................... 14-19
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Parallel Port (General-Purpose I/O)
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MCF5307 User’s Manual
CONTENTS
Chapter 15
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