MCF5307FT90B Freescale Semiconductor, MCF5307FT90B Datasheet - Page 63

• Manufacturer Part Number: MCF5307FT90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307FT90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

2.1.2.1 Instruction Fetch Pipeline (IFP)
Because the fetch and execution pipelines are decoupled by an eight-instruction FIFO
buffer, the IFP can prefetch instructions before the OEP needs them, minimizing stalls.
2.1.2.1.1 Branch Acceleration
Because the IFP and the OEP are decoupled by the instruction buffer, the increased depth
of the IFP is generally hidden from the OEP’s instruction execution. The one exception is
change-of-flow instructions such as unconditional branches or jumps, subroutine calls, and
taken conditional branches. To minimize the effects of the increased depth of the IFP, the
prefetched instruction stream is monitored for change-of-flow opcodes. When certain types
of change-of-flow instructions are detected, the target instruction address is calculated, and
fetching immediately begins in the target stream.
Instruction
Fetch
Pipeline
Operand
Execution
Pipeline
DSOC
AGEX
IAG
IED
IC1
IC2
Freescale Semiconductor, Inc.
Figure 2-1. ColdFire Enhanced Pipeline
IB
For More Information On This Product,
Decode & Select,
Instruction Buffer
Operand Fetch
Fetch Cycle 1
Fetch Cycle 2
Early Decode
Generation,
Generation
Instruction
Instruction
Instruction
Instruction
Address
Address
Execute
FIFO
Chapter 2. ColdFire Core
Go to: www.freescale.com
Features and Enhancements
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