AT91SAM7S64C-AU Atmel, AT91SAM7S64C-AU Datasheet - Page 17
![IC ARM7 MCU 32BIT 64K 64LQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
AT91SAM7S64C-AU
Manufacturer Part Number
AT91SAM7S64C-AU
Description
IC ARM7 MCU 32BIT 64K 64LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7S16-MU.pdf
(779 pages)
Specifications of AT91SAM7S64C-AU
Package / Case
64-LQFP
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
55MHz
Number Of I /o
32
Core Processor
ARM7
Program Memory Type
FLASH
Ram Size
16K x 8
Program Memory Size
64KB (64K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, SPI, SSC, UART/USART, USB
Core Size
16/32-Bit
Core
ARM7TDMI
Package
64LQFP
Device Core
ARM7TDMI
Family Name
AT91
Maximum Speed
55 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
32
Interface Type
SPI/TWI/USART/USB
On-chip Adc
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
AT91SAM7S64B-AU::AT91SAM7S64B-AU
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM7S64C-AU
Manufacturer:
ATMEL
Quantity:
4 300
Part Number:
AT91SAM7S64C-AU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- Current page: 17 of 779
- Download datasheet (11Mb)
7.4
6175K–ATARM–30-Aug-10
Peripheral DMA Controller
• Handles data transfer between peripherals and memories
• Eleven channels: AT91SAM7S512/256/128/64/321/161
• Nine channels: AT91SAM7S32/16
• Low bus arbitration overhead
• Next Pointer management for reducing interrupt latency requirements
• Peripheral DMA Controller (PDC) priority is as follows (from the highest priority to the lowest):
– Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required
– Key-protected program, erase and lock/unlock sequencer
– Single command for erasing, programming and locking operations
– Interrupt generation in case of forbidden operation
– Two for each USART
– Two for the Debug Unit
– Two for the Serial Synchronous Controller
– Two for the Serial Peripheral Interface
– One for the Analog-to-digital Converter
– One Master Clock cycle needed for a transfer from memory to peripheral
– Two Master Clock cycles needed for a transfer from peripheral to memory
wait states
Receive
Receive
Receive
Receive
Receive
Receive
Transmit
Transmit
Transmit
Transmit
Transmit
AT91SAM7S Series Preliminary
DBGU
USART0
USART1
SSC
ADC
SPI
DBGU
USART0
USART1
SSC
SPI
17
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