AT91SAM7S64C-AU Atmel, AT91SAM7S64C-AU Datasheet - Page 52
AT91SAM7S64C-AU
Manufacturer Part Number
AT91SAM7S64C-AU
Description
IC ARM7 MCU 32BIT 64K 64LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7S16-MU.pdf
(779 pages)
Specifications of AT91SAM7S64C-AU
Package / Case
64-LQFP
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
55MHz
Number Of I /o
32
Core Processor
ARM7
Program Memory Type
FLASH
Ram Size
16K x 8
Program Memory Size
64KB (64K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, SPI, SSC, UART/USART, USB
Core Size
16/32-Bit
Core
ARM7TDMI
Package
64LQFP
Device Core
ARM7TDMI
Family Name
AT91
Maximum Speed
55 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
32
Interface Type
SPI/TWI/USART/USB
On-chip Adc
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
AT91SAM7S64B-AU::AT91SAM7S64B-AU
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM7S64C-AU
Manufacturer:
ATMEL
Quantity:
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Part Number:
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Manufacturer:
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12.5.4
12.5.4.1
52
AT91SAM7S Series Preliminary
IEEE 1149.1 JTAG Boundary Scan
JTAG Boundary-scan Register
Table 12-2.
For further details on the Debug Unit, see the Debug Unit section.
IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging
technology.
IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST
and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds
with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1
JTAG-compliant.
It is not possible to switch directly between JTAG and ICE operations. A chip reset must be per-
formed after JTAGSEL is changed.
A Boundary-scan Descriptor Language (BSDL) file is provided to set up testing.
The Boundary-scan Register (BSR) contains 96 bits that correspond to active pins and associ-
ated control signals.
Each AT91SAM7Sxx input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT
bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data
applied to the pad. The CONTROL bit selects the direction of the pad.
Table 12-3.
AT91SAM7S64 Rev C
AT91SAM7S128 Rev A
AT91SAM7S128 Rev B
AT91SAM7S128 Rev C
AT91SAM7S256 Rev A
AT91SAM7S256 Rev B
AT91SAM7S256 Rev C
AT91SAM7S512 Rev A and B
Bit Number
96
95
94
93
92
91
AT91SAM7S Series Debug Unit Chip ID (Continued)
AT91SAM7Sxx JTAG Boundary Scan Register
PA17/PGMD5/AD0
PA18/PGMD6/AD1
Pin Name
Pin Type
IN/OUT
IN/OUT
0x270B0A40
0x270C0740
0x270A0741
0x270A0742
0x270D0940
0x270B0941
0x270B0942
0x27090544
6175K–ATARM–30-Aug-10
Associated BSR
CONTROL
CONTROL
OUTPUT
OUTPUT
INPUT
INPUT
Cells
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