AT91SAM7S64C-AU Atmel, AT91SAM7S64C-AU Datasheet - Page 566

• Manufacturer Part Number: AT91SAM7S64C-AU
• Description: IC ARM7 MCU 32BIT 64K 64LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S64C-AU

• Package / Case: 64-LQFP
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 55MHz
• Number Of I /o: 32
• Core Processor: ARM7
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, SPI, SSC, UART/USART, USB
• Core Size: 16/32-Bit
• Core: ARM7TDMI
• Package: 64LQFP
• Device Core: ARM7TDMI
• Family Name: AT91
• Maximum Speed: 55 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 32
• Interface Type: SPI/TWI/USART/USB
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT91SAM7S64B-AU::AT91SAM7S64B-AU

37.5
Table 37-13. Phase Lock Loop Characteristics
Note:
37.6
Table 37-14. Master Clock Waveform Parameters
37.7
Criteria used to define the maximum frequency of the I/Os:
Table 37-15. I/O Characteristics
566
Symbol
F
F
F
I
Symbol
1/(t
Symbol
FreqMax
PulseminH
PulseminL
FreqMax
PulseminH
• output duty cycle (30%-70%)
• minimum output swing: 100mV to VDDIO - 100mV
• Addition of rising and falling time inferior to 75% of the period
PLL
OUT
OUT
IN
CPMCK
PLL Characteristics
Startup time depends on PLL RC filter. A calculation tool is provided by Atmel.
Master Clock Characteristics
I/O Characteristics
I01
I02
)
AT91SAM7S Series Preliminary
I01
I01
I02
Parameter
Output Frequency:
AT91SAM7S64/32/312/161/16
Output Frequency:
AT91SAM7S512/256/128
Input Frequency
Current Consumption
Parameter
Pin Group 1
Pin Group 1
Pin Group 1
Pin Group 2
Pin Group 2
Parameter
Master Clock Frequency
(1)
(1)
(1)
(2)
(2)
frequency
High Level Pulse Width
High Level Pulse Width
Low Level Pulse Width
frequency
Conditions
Field out of CKGR_PLL is:
Field out of CKGR_PLL is:
Active mode
Standby mode
Conditions
Conditions
3.3V domain
1.8V domain
3.3V domain
1.8V domain
3.3V domain
1.8V domain
3.3V domain
1.8V domain
3.3V domain
1.8V domain
00
10
00
10
(4)
(5)
(4)
(5)
(4)
(5)
(4)
(5)
(4)
(5)
Min
Min
Min
150
150
110
110
80
80
40
40
20
36
1
Typ
Max
Max
12.5
55
4.5
25
14
6175K–ATARM–30-Aug-10
Max
160
200
160
180
32
4
1
Units
MHz
MHz
MHz
MHz
Units
MHz
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
MHz
MHz
Unit
mA
µA