AT91SAM7S64C-AU Atmel, AT91SAM7S64C-AU Datasheet - Page 592

• Manufacturer Part Number: AT91SAM7S64C-AU
• Description: IC ARM7 MCU 32BIT 64K 64LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S64C-AU

• Package / Case: 64-LQFP
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 55MHz
• Number Of I /o: 32
• Core Processor: ARM7
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, SPI, SSC, UART/USART, USB
• Core Size: 16/32-Bit
• Core: ARM7TDMI
• Package: 64LQFP
• Device Core: ARM7TDMI
• Family Name: AT91
• Maximum Speed: 55 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 32
• Interface Type: SPI/TWI/USART/USB
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT91SAM7S64B-AU::AT91SAM7S64B-AU

40.2
Table 40-1.
592
Part
Chip ID
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
EFC
JTAG
MCK
NVM Bits
PIO
PIO
PIO
PMC
PMC
PWM
PWM
PWM
PWM
Errata Summary by Product and Revision or Manufacturing Number
AT91SAM7S Series Preliminary
Errata
Wrong Chip ID Value
DRDY Bit Cleared
DRDY not Cleared on Disable
DRDY Possibly Skipped due to CDR Read
Possible Skip on DRDY when Disabling a
Channel
GOVRE Bit is not Updated
GOVRE Bit is not Set when Reading CDR
GOVRE Bit is not Set when Disabling a Channel
OVRE Flag Behavior
EOC Set although Channel Disabled
Spurious Clear of EOC Flag
Sleep Mode
Embedded Flash Access Time 1
Embedded Flash Access Time 2
Recommendation for TDI Pin
Limited Master Clock Frequency Ranges
Leakage on PA17 - PA20
Electrical Characteristics on NRST and PA0-
PA16 and PA21-31
Drive Low NRST, PA0-PA16 and PA21-PA31
Slow Clock Selected in PMC and a Transition
Occurs on PA1
Programming CSS in PMC_MCKR Register
Update when PWM_CCNTx = 0 or 1
Update when PWM_CPRDx = 0
Counter Start Value
Constraints on Duty Cycle Value
Write/Erase Cycles Number
Errata Summary Table
Revision or Manufacturing Number
AT91SAM7Sx Product
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6175K–ATARM–30-Aug-10
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