AT91SAM7S64C-AU Atmel, AT91SAM7S64C-AU Datasheet - Page 527

• Manufacturer Part Number: AT91SAM7S64C-AU
• Description: IC ARM7 MCU 32BIT 64K 64LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S64C-AU

• Package / Case: 64-LQFP
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 55MHz
• Number Of I /o: 32
• Core Processor: ARM7
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, SPI, SSC, UART/USART, USB
• Core Size: 16/32-Bit
• Core: ARM7TDMI
• Package: 64LQFP
• Device Core: ARM7TDMI
• Family Name: AT91
• Maximum Speed: 55 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 32
• Interface Type: SPI/TWI/USART/USB
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT91SAM7S64B-AU::AT91SAM7S64B-AU

35.6.10
Register Name:
Access Type:
WARNING: Due to synchronization between MCK and UDPCK, the software application must wait for the end of the write
operation before executing another write by polling the bits which must be set/cleared.
Note:
• TXCOMP: Generates an IN Packet with Data Previously Written in the DPR
This flag generates an interrupt while it is set to one.
Write (Cleared by the firmware):
0 = Clear the flag, clear the interrupt.
1 = No effect.
Read (Set by the USB peripheral):
0 = Data IN transaction has not been acknowledged by the Host.
1 = Data IN transaction is achieved, acknowledged by the Host.
After having issued a Data IN transaction setting TXPKTRDY, the device firmware waits for TXCOMP to be sure that the
host has acknowledged the transaction.
6175K–ATARM–30-Aug-10
//! Clear flags of UDP UDP_CSR register and waits for synchronization
#define Udp_ep_clr_flag(pInterface, endpoint, flags) { \
//! Set flags of UDP UDP_CSR register and waits for synchronization
#define Udp_ep_set_flag(pInterface, endpoint, flags) { \
EPEDS
DIR
31
23
15
–
7
pInterface->UDP_CSR[endpoint] &= ~(flags); \
while ( (pInterface->UDP_CSR[endpoint] & (flags)) == (flags) ); \
}
pInterface->UDP_CSR[endpoint] |= (flags); \
while ( (pInterface->UDP_CSR[endpoint] & (flags)) != (flags) ); \
}
In a preemptive environment, set or clear the flag and wait for a time of 1 UDPCK clock cycle and 1peripheral clock cycle. How-
ever, RX_DATA_BLK0, TXPKTRDY, RX_DATA_BK1 require wait times of 3 UDPCK clock cycles and 3 peripheral clock cycles
before accessing DPR.
UDP Endpoint Control and Status Register
RX_DATA_
BK1
30
22
14
UDP_ CSRx [x = 0..Y]
Read-write
–
–
6
FORCE
STALL
29
21
13
–
–
5
TXPKTRDY
28
20
12
–
–
4
RXBYTECNT
AT91SAM7S Series Preliminary
STALLSENT
ISOERROR
DTGLE
27
19
11
–
3
RXSETUP
26
18
10
2
RXBYTECNT
RX_DATA_
EPTYPE
BK0
25
17
9
1
TXCOMP
24
16
8
0
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