XR17V358IB176-F Exar Corporation, XR17V358IB176-F Datasheet - Page 10

• Manufacturer Part Number: XR17V358IB176-F
• Description: IC UART PCIE OCTAL 176FPBGA
• Manufacturer: Exar Corporation

Specifications of XR17V358IB176-F

• Number Of Channels: 1, UART
• Package / Case: 176-LFBGA
• Features: *
• Fifo's: 256 Byte
• Protocol: RS485
• Voltage - Supply: 1.2V, 3.3V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 25 Mbps
• Supply Current: 120 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• No. Of Channels: 8
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: BGA
• No. Of Pins: 176
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 1016-1296 - EVAL BOARD FOR XR17V358-E81016-1295 - EVAL BOARD FOR XR17V358-E41016-1293 - EVAL BOARD FOR XR17V358
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 1016-1294

XR17V358
HIGH PERFORMANCE OCTAL PCI EXPRESS UART
The XR17V358 UART register set is very similar to the previous generation PCI UARTs. This makes the V358
software compatible with the previous generation PCI UARTs. Minimal changes are needed to the software
driver of an existing Exar PCI UART driver so that it can be used with the V358 PCIe UART.
There are three different sets of registers as shown in
Registers is needed for plug-and-play auto-configuration. This auto-configuration feature makes installation
very easy into a PCI system and it is part of the PCI local bus specification. The second register set is the
Device Configuration Registers that are also accessible directly from the PCI bus for programming general
operating conditions of the device and monitoring the status of various functions common to all eight channels.
These functions include all 8 channel UARTs’ interrupt control and status, 16-bit general purpose timer control
and status, multipurpose inputs/outputs control and status, sleep mode, soft-reset, and device identification
and revision. And lastly, each UART channel has its own set of internal UART Configuration Registers for its
own operation control and status reporting. All 8 sets of channel registers are embedded inside the device
configuration registers space, which provides faster access. The second and third set of registers are mapped
into 8K of the PCI bus memory address space. The following paragraphs describe all 3 sets of registers in
detail.
The PCI local bus configuration space registers are responsible for setting up the device’s operating
environment in the PCI local bus. The pre-defined operating parameters of the device is read by the PCI bus
plug-and-play auto-configuration manager in the operating system. After the PCI bus has collected all data
from every device/card on the bus, it defines and downloads the memory mapping information to each device/
card about their individual operation memory address location and conditions. The operating memory mapped
address location is downloaded into the Base Address Register (BAR) register, located at an address offset of
0x10 in the configuration space. Custom modification of certain registers is possible by using an external
93C46 EEPROM. The EEPROM contains the device vendor and sub-vendor data, along with 6 other words of
information (see
F
1.0 XR17V358 INTERNAL REGISTERS
1.1
IGURE
D e v ic e C o n fig u ra tio n a n d
R e g is te rs a re m a p p e d o n
b y te o f m e m o ry a d d re s s
U A R T [7 :0 ] C o n fig u ra tio n
R e g is te r (B A R ) in a 8 K -
P C I L o c a l B u s
to th e B a s e A d d re s s
In te rfa c e
3. T
PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
s p a c e
HE
XR17V358 R
“Section 1.2, EEPROM Interface” on page
EGISTER
S
ETS
C o n fig u ra tio n S p a c e
R e g is te rs fo r P lu g -
a n d -P la y A u to
P C I L o c a l B u s
C o n fig u ra tio n
C h a n n e l 2
C h a n n e l 3
C h a n n e l 4
C h a n n e l 5
C h a n n e l 6
C h a n n e l 7
T IM E R , R E G
C h a n n e l 0
C h a n n e l 1
C h a n n e l 0
IN T , M P IO ,
10
Figure
14) required by the auto-configuration setup.
3. The PCI Local Bus Configuration Space
0 x 0 C 0 0
0 x 0 0 0 0
0 x 0 0 8 0
0 x 0 4 0 0
0 x 0 8 0 0
0 x 1 0 0 0
0 x 1 C 0 0
0 x 1 4 0 0
0 x 1 8 0 0
0 x 1 F F F
V e n d o r a n d S u b -v e n d o r ID
a n d P ro d u c t M o d e l N u m b e r
in E x te rn a l E E P R O M
D e v ic e C o n fig u ra tio n R e g is te rs
1 6 5 5 0 C o m p a tib le a n d E X A R
S le e p , R e s e t, D V ID , D R E V
U A R T [7 :0 ] C o n fig u ra tio n
1 6 -b it T im e r/C o u n te r,
8 c h a n n e l In te rru p ts ,
E n h a n c e d R e g is te rs
M u ltip u rp o s e I/O s ,
R e g is te rs
REV. 1.0.2