XR17V358IB176-F Exar Corporation, XR17V358IB176-F Datasheet - Page 44
![IC UART PCIE OCTAL 176FPBGA](/photos/28/69/286931/176-lfbga_sml.jpg)
XR17V358IB176-F
Manufacturer Part Number
XR17V358IB176-F
Description
IC UART PCIE OCTAL 176FPBGA
Manufacturer
Exar Corporation
Datasheet
1.XR17V358IB176-F.pdf
(68 pages)
Specifications of XR17V358IB176-F
Number Of Channels
1, UART
Package / Case
176-LFBGA
Features
*
Fifo's
256 Byte
Protocol
RS485
Voltage - Supply
1.2V, 3.3V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Data Rate
25 Mbps
Supply Current
120 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
No. Of Channels
8
Uart Features
Tx/Rx FIFO Counters
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
BGA
No. Of Pins
176
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
1016-1296 - EVAL BOARD FOR XR17V358-E81016-1295 - EVAL BOARD FOR XR17V358-E41016-1293 - EVAL BOARD FOR XR17V358
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
1016-1294
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XR17V358IB176-F
Manufacturer:
EXAR
Quantity:
1 700
Company:
Part Number:
XR17V358IB176-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
XR17V358IB176-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
A
XR17V358
HIGH PERFORMANCE OCTAL PCI EXPRESS UART
N
The transmitter section comprises of a 256 bytes of FIFO, a byte-wide Transmit Holding Register (THR) and an
8-bit Transmit Shift Register (TSR). THR receives a data byte from the host (non-FIFO mode) or a data byte
from the FIFO when the FIFO is enabled by FCR bit [0]. TSR shifts out every data bit with the 16X or 8X
internal clock. A bit time is 16 or 8 clock periods. The transmitter sends the start bit followed by the number of
data bits, inserts the proper parity bit if enable, and adds the stop bit(s). The status of the THR and TSR are
reported in the Line Status Register (LSR bit [6:5]).
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (bit [0]) becomes first data bit to go out. The THR is also the
input register to the transmit FIFO of 256 bytes when FIFO operation is enabled by FCR bit[0]. A THR empty
interrupt can be generated when it is enabled in IER bit [1].
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit [5]) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit [1]) when it is
enabled by IER bit [1]. The TSR flag (LSR bit [6]) is set when TSR becomes completely empty.
1 0 0 1
1 0 1 0
1 0 1 0
1 0 1 1
1 0 1 1
1 1 0 0
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
A3-A0
3.6
T
3.6.1
3.6.2
DDRESS
OTE
ABLE
:
compatibility during Internal loopback, see
14: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION.
MCR bits [3:2] (OP1 and OP2 outputs) are not available in the XR17V358. They are present for 16C550
Transmitter
TXTRG
RXCNT
RXTRG
XCHAR
TXCNT
XOFF1
XOFF2
XON1
XON2
N
Transmit Holding Register (THR)
Transmitter Operation in non-FIFO Mode
R
EFR
AME
EG
W
R
R/W
EAD
W
W
W
W
W
W
RITE
R
R
R
/
Enable
B
Bit [7]
Bit [7]
Bit [7]
Bit [7]
Bit [7]
Bit [7]
Bit [7]
Bit [7]
CTS/
Auto
DSR
IT
0
[7]
Enable
B
Bit [6]
Bit [6]
Bit [6]
Bit [6]
Bit [6]
Bit [6]
Bit [6]
Bit [6]
RTS/
Auto
DTR
IT
0
[6]
Special
B
Select
Bit [5]
Bit [5]
Bit [5]
Bit [5]
Bit [5]
Bit [5]
Bit [5]
Bit [5]
Char
IT
Figure 12
0
[5]
MCR[7:5],
FCR[5:4],
IER [7:5],
ISR [5:4],
44
Enable
B
Bit [4]
Bit [4]
Bit [4]
Bit [4]
Bit [4]
Bit [4]
Bit [4]
Bit [4]
MSR
.
IT
0
[4]
Indicator
TX Xon
B
Bit [3]
Bit [3]
Bit [3]
Bit [3]
Bit [3]
Bit [3]
Bit [3]
Bit [3]
Bit [3]
ware
Soft-
Flow
Cntl
IT
[3]
Indicator
TX Xoff
B
Bit [2]
Bit [2]
Bit [2]
Bit [2]
Bit [2]
Soft-
ware
Flow
Bit-2
Bit-2
Bit-2
Bit-2
Cntl
IT
[2]
S
HADED BITS ARE ENABLED BY
Xon Det.
Indicator
B
Bit [1]
Bit [1]
Bit [1]
Bit [1]
Bit [1]
Bit [1]
Bit [1]
Bit [1]
Bit [1]
ware
Soft-
Flow
Cntl
IT
[1]
Flow Cntl
Software
Xoff Det.
Indicator
B
Bit [0]
Bit [0]
Bit [0]
Bit [0]
Bit [0]
Bit [0]
Bit [0]
Bit [0]
Bit [0]
IT
[0]
REV. 1.0.2
EFR B
after read
Self clear
C
OMMENT
IT
-4.