XR17V358IB176-F Exar Corporation, XR17V358IB176-F Datasheet - Page 58

• Manufacturer Part Number: XR17V358IB176-F
• Description: IC UART PCIE OCTAL 176FPBGA
• Manufacturer: Exar Corporation

Specifications of XR17V358IB176-F

• Number Of Channels: 1, UART
• Package / Case: 176-LFBGA
• Features: *
• Fifo's: 256 Byte
• Protocol: RS485
• Voltage - Supply: 1.2V, 3.3V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 25 Mbps
• Supply Current: 120 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• No. Of Channels: 8
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: BGA
• No. Of Pins: 176
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 1016-1296 - EVAL BOARD FOR XR17V358-E81016-1295 - EVAL BOARD FOR XR17V358-E41016-1293 - EVAL BOARD FOR XR17V358
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 1016-1294

XR17V358
HIGH PERFORMANCE OCTAL PCI EXPRESS UART
MSR[3]: Delta CD# Input Flag
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•
MSR[2]: Delta RI# Input Flag
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•
MSR[1]: Delta DSR# Input Flag
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•
MSR[0]: Delta CTS# Input Flag
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•
The upper four bits [7:4] of this register set the delay in number of bits time for the auto RS-485 turn around
from transmit to receive.
MSR [7:4]: Auto RS485 Turn-Around Delay (requires EFR bit [4]=1)
When Auto RS485 feature is enabled (FCTR bit [5]=1) and RTS#/DTR# output is connected to the enable input
of a RS-485 transceiver. These 4 bits select from 0 to 15 bit-time delay after the end of the last stop-bit of the
last transmitted character. This delay controls when to change the state of RTS#/DTR# output. This delay is
very useful in long-cable networks.
4.11
Logic 0 = No change on CD# input (default).
Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit [3]).
Logic 0 = No change on RI# input (default).
Logic 1 = The RI# input has changed from a LOW to a HIGH, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit [3]).
Logic 0 = No change on DSR# input (default).
Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit [3]).
Logic 0 = No change on CTS# input (default).
Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit [3]).
Modem Status Register (MSR) - Write Only
Table 18
shows the selection. The bits are enabled by EFR bit-4.
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REV. 1.0.2