AD9869-EBZ Analog Devices Inc, AD9869-EBZ Datasheet - Page 12

• Manufacturer Part Number: AD9869-EBZ
• Description: BOARD EVAL FOR AD9869
• Manufacturer: Analog Devices Inc
• Type: ADC + DAC, Codec, Front End for RFr

Specifications of AD9869-EBZ

• Contents: Board
• For Use With/related Products: AD9869
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9869
SERIAL PORT
Table 10. SPI Register Mapping
Address
(Hex)
SPI PORT CONFIGURATION AND SOFTWARE RESET
0x00
POWER CONTROL REGISTERS (Via PWRDWN Pin)
0x01
0x02
HALF-DUPLEX POWER CONTROL
0x03
PLL CLOCK MULTIPLIER/SYNTHESIZER CONTROL
0x04
0x05
0x06
Rx PATH CONTROL
0x07
0x08
Bit
7
6
5
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7:3
2
1
0
4
3:2
1:0
2
1
0
7:6
5
4
3:2
1
0
5
4
0
7:0
1
Description
4-Wire SPI
SPI LSB First
Software Reset
CLK Synthesizer
TxDAC/IAMP
Tx Digital
REF
ADC CML
ADC
PGA Bias
RxPGA
CLK Synthesizer
TxDAC/IAMP
Tx Digital
REF
ADC CML
ADC
PGA Bias
RxPGA
Tx OFF Delay
Rx_TXEN
Tx PWRDN
Rx PWRDN
f
PLL Divide-N
PLL Multiplier-M
OSCIN to RXCLK
Invert RXCLK
Disable RXCLK
CLKOUT2 Divide
CLKOUT2 Invert
CLKOUT2 Disable
CLKOUT1 Divide
CLKOUT1 Invert
CLKOUT1 Disable
Initiate Offset Cal.
Rx Low Power
Enable Rx LPF
Rx Filter Target
Cutoff Frequency
ADC
from PLL
Width
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
5
1
1
1
1
2
2
1
1
1
2
1
1
2
1
1
1
1
1
8
CONFIG = 0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0xFF
0xFF
0xFF
0xFF
0
00
01
0
0
0
01
0
0
01
0
0
0
0
1
0x80
(Half-Duplex)
MODE = 0
Rev. 0 | Page 12 of 36
Power-Up Default Value
CONFIG = 1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
00
10
0
0
0
01
0
0
01
0
0
0
1
1
0x61
0xFF
0xFF
0xFF
0xFF
CONFIG = 0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
00
01
0
0
01
0
0
01
0
0
0
0x80
(Full-Duplex)
0
0
1
N/A
N/A
N/A
N/A
MODE = 1
Comments
Default SPI configuration is 3-wire,
MSB first.
PWRDWN = 0.
Default setting is for all blocks powered on.
PWRDWN = 1.
Default setting is for all functional blocks
powered down except PLL.
Default setting is for TXEN input to
control power-on/power-off of Tx/Rx
path. Tx driver delayed by 31 1/f
cycles.
Full-duplex RXCLK normally at nibble rate.
Default setting is CLKOUT2 and
CLKOUT1 enabled with divide-by-2.
Default setting has LPF on.
Rx path at nominal power bias setting for
CONFIG = 0 and low power for CONFIG = 1.
Refer to the Low-Pass Filter section.
DATA
clock