AD9869-EBZ Analog Devices Inc, AD9869-EBZ Datasheet - Page 27

• Manufacturer Part Number: AD9869-EBZ
• Description: BOARD EVAL FOR AD9869
• Manufacturer: Analog Devices Inc
• Type: ADC + DAC, Codec, Front End for RFr

Specifications of AD9869-EBZ

• Contents: Board
• For Use With/related Products: AD9869
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 20 shows the SPI registers pertaining to the ADC.
Table 20. SPI Registers for Rx ADC
Address (Hex)
0x04
0x07
0x13
Bit
4
4
2:0
ADC clock from PLL.
ADC low power mode.
ADC power bias adjust.
Description
Rev. 0 | Page 27 of 36
AGC TIMING CONSIDERATIONS
When implementing a digital AGC timing loop, it is important
to consider the Rx path latency and settling time of the Rx path
in response to a change in gain setting. While the RxPGA
settling time may also show a slight dependency on the LPF
cutoff frequency, the ADC pipeline delay, along with the ADIO
bus interface, presents a more significant delay. The amount of
delay or latency is dependent on whether a half-duplex or full-
duplex is selected. An impulse response at the RxPGA input can
be observed after 10.0 ADC clock cycles (1/f
half-duplex interface, and 10.5 ADC clock cycles in the case of a
full-duplex interface. This latency, along with the RxPGA settling
time, should be considered to ensure stability of the AGC loop.
ADC
) in the case of a
AD9869