AD9869-EBZ Analog Devices Inc, AD9869-EBZ Datasheet - Page 13

• Manufacturer Part Number: AD9869-EBZ
• Description: BOARD EVAL FOR AD9869
• Manufacturer: Analog Devices Inc
• Type: ADC + DAC, Codec, Front End for RFr

Specifications of AD9869-EBZ

• Contents: Board
• For Use With/related Products: AD9869
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Address
(Hex)
Tx/Rx PATH GAIN CONTROL
0x09
0x0A
TxPGA AND RxPGA CONTROL
0x0B
Tx DIGITAL FILTER AND INTERFACE
0x0C
Rx INTERFACE AND ANALOG/DIGITAL LOOPBACK
0x0D
DIGITAL OUTPUT DRIVE STRENGTH, TxDAC OUTPUT, AND REV ID
0x0E
0x0F
Tx IAMP GAIN AND BIAS CONTROL
0x10
0x12
0x13
1
2
Bits that are undefined should always be assigned a 0.
Full-duplex only.
Bit
6
5:0
6
5:0
6
5
3
2
1
7:6
4
3
2
1
0
7
6
5
4
3
2
1
0
7
0
3:0
7
2:0
6:4
2:0
7:5
4:3
2:0
1
Description
Enable SPI Rx Gain
Rx Gain Code
Enable SPI Tx Gain
Tx Gain Code
PGA Code for Tx
PGA Code for Rx
Force Gain Strobe
Rx Gain on Tx Port
3-Bit RxPGA Port
Interpolation
Factor
Invert
TXEN/TXSYNC
Tx 5/5 Nibble
LS Nibble First
TXCLK Neg. Edge
Twos Complement
Analog Loopback
Digital Loopback
Rx Port Three-State
Invert
RXEN/RXSYNC
Rx 5/5 Nibble
LS Nibble First
RXCLK Neg. Edge
Twos Complement
Low Digital Drive
Strength
TxDAC Output
REV ID Number
Select Tx Gain
N
Standing Current
I
Current
CPGA Bias Adjust
SPGA Bias Adjust
ADC Bias Adjust
OFF1
Standing
2
2
2
Width
1
6
1
6
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
1
3
3
3
3
2
4
CONFIG = 0
0x00
0x00
0x7F
0x7F
0
1
0
0
0
01
0
N/A
N/A
0
0
0
0
N/A
0
N/A
N/A
0
0
0
0
0x00
0x04
0x04
0x01
0x01
0x00
(Half-Duplex)
MODE = 0
Rev. 0 | Page 13 of 36
Power-Up Default Value
CONFIG = 1
0x00
0x00
0x7F
0x7F
0
1
0
0
1
00
0
N/A
N/A
0
0
0
0
N/A
0
N/A
N/A
0
0
0
0
0x00
0x04
0x04
0x01
0x01
0x00
(Full-Duplex)
CONFIG = 0
0x00
0x00
0x7F
0x7F
0
1
0
1
0
01
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0x00
0x04
0x04
0x01
0x01
0x00
MODE = 1
Comments
Default setting is for hardware Rx gain
code via PGA or Tx data port.
Default setting is for Tx gain code via
SPI control.
Default setting is RxPGA control active via
PGA port.
Default setting is 2× interpolation with
LPF response. Data format is straight
binary for half-duplex and twos
complement for full-duplex interface.
Data format is straight binary for
half-duplex and twos complement for
full-duplex interface. Analog loopback:
ADC Rx data fed back to TxDAC. Digital
loopback: Tx input data to Rx output port.
Default setting is for high drive strength
and IAMP enabled.
N = 0, 1, 2, 3, 4.
Standing current.
Current bias setting for Rx path’s
functional blocks. Refer to the Power
Reduction Options section.
AD9869