AD9869-EBZ Analog Devices Inc, AD9869-EBZ Datasheet - Page 8

• Manufacturer Part Number: AD9869-EBZ
• Description: BOARD EVAL FOR AD9869
• Manufacturer: Analog Devices Inc
• Type: ADC + DAC, Codec, Front End for RFr

Specifications of AD9869-EBZ

• Contents: Board
• For Use With/related Products: AD9869
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9869
HALF-DUPLEX DATA INTERFACE (ADIO PORT) TIMING SPECIFICATIONS
AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted.
Table 6.
Parameter
READ OPERATION
WRITE OPERATION (See Figure 8)
1
2
FULL-DUPLEX DATA INTERFACE (Tx AND Rx PORT) TIMING SPECIFICATIONS
AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted.
Table 7.
Parameter
Tx PATH INTERFACE (See Figure 12)
Rx PATH INTERFACE
1
2
See the Explanation of Test Levels section.
C
See the Explanation of Test Levels section.
C
LOAD
LOAD
Output Data Rate
Three-State Output Enable Time (t
Three-State Output Disable Time (t
Rx Data Valid Time (t
Rx Data Output Delay (t
Input Data Rate (2× Interpolation)
Input Data Rate (4× Interpolation)
Tx Data Setup Time (t
Tx Data Hold Time (t
Latch Enable Time (t
Latch Disable Time (t
Input Nibble Rate (2× Interpolation)
Input Nibble Rate (4× Interpolation)
Tx Data Setup Time (t
Tx Data Hold Time (t
Output Nibble Rate
Rx Data Valid Time (t
Rx Data Hold Time (t
= 5 pF for digital data outputs.
= 5 pF for digital data outputs.
2
(See Figure 9)
2
(See Figure 13)
DH
EN
DH
VT
DV
DH
DIS
DS
DS
)
)
)
)
)
)
)
)
)
OD
)
PZL
PLZ
)
)
Temp
Full
Full
Full
Full
Full
Full
Full
Rev. 0 | Page 8 of 36
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level
II
II
II
II
II
II
II
Test Level
II
II
II
II
II
II
II
II
II
II
II
1
1
Min
80
40
2.5
1.5
40
3
0
Min
20
1.5
40
20
1
2.5
Typ
Typ
Max
160
100
160
Max
80
3
3
4
80
50
3
3
Unit
MSPS
MSPS
ns
ns
MSPS
ns
ns
Unit
MSPS
ns
ns
ns
ns
MSPS
MSPS
ns
ns
ns
ns