AD9869-EBZ Analog Devices Inc, AD9869-EBZ Datasheet - Page 26

• Manufacturer Part Number: AD9869-EBZ
• Description: BOARD EVAL FOR AD9869
• Manufacturer: Analog Devices Inc
• Type: ADC + DAC, Codec, Front End for RFr

Specifications of AD9869-EBZ

• Contents: Board
• For Use With/related Products: AD9869
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9869
The following scaling factor can be applied to the previous
formula to compensate for the RxPGA gain setting on f
This scaling factor reduces the calculated f
increases. Applications that need to maintain a minimum cutoff
frequency, f
determine the scaling factor for the highest RxPGA gain setting
to be used. Next, the f
factor to normalize to the 0 dB RxPGA gain setting, f
Equation 5 can then be used to calculate the target value.
The LPF frequency response shows a slight sensitivity to
temperature, as shown in Figure 30. Applications sensitive to
temperature drift can recalibrate the LPF by rewriting the target
value to Register 0x08.
Figure 30. f
Scale Factor = 1 − (RxPGA in dB)/382
35
30
25
20
15
Figure 29. Measured and Calculated f
35
33
31
29
27
25
23
21
19
17
15
96
48
50MSPS MEASURED
50MSPS CALCULATED
−3 dB_MIN
−3 dB
112
64
Temperature Drift for f
80
128
, for all RxPGA gain settings should first
TARGET-DECIMAL EQUIVALENT
f
TARGET-DECIMAL EQUIVALENT
ADC
−3 dB_MIN
96
144
= 50 MSPS and 80 MSPS
f
OUT
112
f
OUT
ACTUAL 80MHz AND –40°C
160
f
should be divided by this scale
OUT
128
ACTUAL 80MHz AND +25°C
ACTUAL 80MHz AND +85°C
176
ADC
144
= 80 MSPS and RxPGA = 0 dB
80MSPS MEASURED
−3 dB
80MSPS CALCULATED
160
192
vs. Target Value for
−3 dB
176
208
as the RxPGA
192
224
208
−3 dB_0 dB
−3 dB
240
224
:
.
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ANALOG-TO-DIGITAL CONVERTER (ADC)
The AD9869 features a 12-bit analog-to-digital converter
(ADC) capable of up to 80 MSPS. As shown in Figure 24, the
ADC is driven by the SPGA stage, which performs both the
sample-and-hold and the fine gain adjust functions. A buffer
amplifier (not shown) isolates the last CPGA gain stage from
the dynamic load presented by the SPGA stage. The full-scale
input span of the ADC is 2 V p-p, and depending on the PGA
gain setting, the full-scale input span into the SPGA is adjustable
from 1 V to 2 V in 1 dB increments.
A pipelined, multistage ADC architecture is used to achieve high
sample rates while consuming low power. The ADC distributes the
conversion over several smaller ADC subblocks, refining the
conversion with progressively higher accuracy as it passes the
results from stage to stage on each clock edge. The ADC typically
performs best when driven internally by a 50% duty cycle clock.
The ADC power consumption can be reduced by 25 mA with
minimal effect on its performance by setting Bit 4 of Register 0x07.
Alternative power bias settings are also available via Register 0x13,
as discussed in the Power Control and Dissipation section.
Lastly, the ADC can be completely powered down for half-duplex
operation, further reducing the peak power consumption of the
AD9869.
The ADC has an internal voltage reference and reference amplifier
as shown in Figure 31. The internal band gap reference generates
a stable 1 V reference level that is converted to a differential 1 V
reference centered about midsupply (AVDD/2). The outputs of
the differential reference amplifier are available at the REFT and
REFB pins and must be properly decoupled for optimum perform-
ance. The REFT and REFB pins are conveniently situated at
the corners of the LFCSP package such that C1 (0603 type)
can be placed directly across its pins. C3 and C4 can be placed
underneath C1, and C2 (10 μF tantalum) can be placed furthest
from the package.
Figure 31. ADC Reference and Decoupling
1.0V
VIEW
TOP
ADCs
TO
REFT
REFB
C1
C4
C1
0.1µF
C2
C3
C3
0.1µF
C4
0.1µF
C2
10µF