AD9869-EBZ Analog Devices Inc, AD9869-EBZ Datasheet - Page 14

• Manufacturer Part Number: AD9869-EBZ
• Description: BOARD EVAL FOR AD9869
• Manufacturer: Analog Devices Inc
• Type: ADC + DAC, Codec, Front End for RFr

Specifications of AD9869-EBZ

• Contents: Board
• For Use With/related Products: AD9869
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9869
REGISTER MAP DESCRIPTION
The AD9869 contains a set of programmable registers (see
Table 10) that are used to optimize its numerous features,
interface options, and performance parameters from its default
register settings. Registers pertaining to similar functions have
been grouped together and assigned adjacent addresses to
minimize the update time when using the multibyte serial port
interface (SPI) read/write feature. Bits that are undefined within
a register should be assigned a 0 when writing to that register.
The default register settings are intended to allow some applica-
tions to operate without using an SPI. The AD9869 can be
configured to support a half- or full-duplex digital interface via
the MODE pin, with each interface having two possible default
register settings determined by the setting of the CONFIG pin.
For instance, applications that need to use only the Tx or Rx path
functionality can configure the AD9869 for a half-duplex interface
(MODE = 0), and use the TXEN pin to select between the Tx or
Rx signal path with the unused path remaining in a reduced
power state. The CONFIG pin can be used to select the default
interpolation ratio of the Tx path and RxPGA gain mapping.
SERIAL PORT INTERFACE (SPI)
The serial port of the AD9869 has 3-wire or 4-wire SPI capability
allowing read/write access to all registers that configure the device’s
internal parameters. Registers pertaining to the SPI are listed in
Table 11. The default 3-wire serial communication port consists
of a clock (SCLK), serial port enable ( SEN ), and a bidirectional
data (SDIO) signal. SEN is an active low, control gating, read
and write cycle. When SEN is high, SDO and SDIO are three-
stated. The inputs to SCLK, SEN , and SDIO contain a Schmitt
trigger with a nominal hysteresis of 0.4 V centered about
DRVDD/2. The SDO pin remains three-stated in a 3-wire SPI
interface.
Table 11. SPI Registers Pertaining to SPI Options
Address (Hex)
0x00
A 4-wire SPI can be enabled by setting the 4-wire SPI bit high,
causing the output data to appear on the SDO pin instead of on the
SDIO pin. The SDIO pin serves as an input-only throughout the
read operation. Note that the SDO pin is active only during the
transmission of data and remains three-stated at any other time.
Bit
7
6
Description
Enable 4-wire SPI.
Enable SPI LSB first.
Rev. 0 | Page 14 of 36
An 8-bit instruction header must accompany each read and
write operation. The instruction header is shown in Table 12.
The MSB is an R/ W indicator bit with logic high indicating a
read operation. The next two bits, N1 and N0, specify the
number of bytes (one to four bytes) to be transferred during the
data transfer cycle. The remaining five bits specify the address
bits to be accessed during the data transfer portion. The data
bits immediately follow the instruction header for both read
and write operations.
Table 12. Instruction Header Information
MSB
17
R/W
The AD9869 serial port can support both MSB (most significant
bit) first and LSB (least significant bit) first data formats. Figure 3
illustrates how the serial port words are built for the MSB first
and Figure 4 illustrates LSB first modes. The bit order is
controlled by the SPI LSB first bit (Register 0x00, Bit 6). The
default value is 0, MSB first. Multibyte data transfers in MSB
format can be completed by writing an instruction byte that
includes the register address of the last address to be accessed.
The AD9869 automatically decrements the address for each
successive byte required for the multibyte communication cycle.
When the SPI LSB first bit is set high, the serial port interprets
both instruction and data bytes LSB first. Multibyte data transfers
in LSB format can be completed by writing an instruction byte
that includes the register address of the first address to be accessed.
The AD9869 automatically increments the address for each
successive byte required for the multibyte communication cycle.
SDATA
SDATA
SCLK
SCLK
SEN
SEN
R/W
A0
16
N1
A1
N1
INSTRUCTION CYCLE
INSTRUCTION CYCLE
A2 A3
N2
15
N0
A4
Figure 3. SPI Timing, MSB First
Figure 4. SPI Timing, LSB First
A3
A4 N2 N1 R/W D0 1 D1 1
A2
14
A4
A1 A0
13
A3
D7 1 D6 1
DATA TRANSFER CYCLE
DATA TRANSFER CYCLE
12
A2
11
A1
D1 N
D6 N D7 N
D0 N
LSB
10
A0